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1 datasheet 2-phase boost controller with integrated drivers isl78227 the isl78227 is an automotive grade (aec-q100 grade 1), 2-phase 55v synchronous boost co ntroller intended to simplify the design of high power boos t applications. it integrates strong half-bridge drivers, an an alog/digital tracking input and comprehensive protection functions. the isl78227 enables a simple, modular design for systems requiring power and thermal scalab ility. it offers peak-current mode control for fast line resp onse and simple compensation. its synchronous 2-phase architecture enables it to support higher current while reducing the size of input and output capacitors. the integrated drivers feature programmable adaptive dead time control offe ring flexibility in power stage design. isl78227 offers a 90output clock and supports 1-, 2- and 4-phases. the isl78227 offers a highly robust solution for the most demanding environments. its unique soft-start control prevents large negative current even in extreme cases, such as a restart under high output prebias on high volume capacitances. it also offers two levels of cycle-by-cycle overcurrent protection, average current limiting, input ovp, output uvp/ovp and internal otp. in the event of a fault, the fault protection respon se can be selected to be latch-off or hiccup recovery. also integrated are several func tions that ease system design. a unique tracking input is availa ble that can control the output voltage, allowing it to track either a digital duty cycle (pwm) signal or an analog referenc e. the isl78227 provides input average current limiting so the system can deliver transient bursts of high load current while limiting the average current to avoid overheating. features ? input/output voltage range: 5v to 55v, withstands 60v transients ? supports synchronous or standard boost topology ? peak current mode control with adjustable slope compensation ? secondary average current control loop ? integrated 5v 2a sourcing/3 a sinking n-channel mosfet drivers ? switching frequency: 50khz to 1.1mhz per phase ? external synchronization ? programmable minimum duty cycle ? programmable adaptive dead time control ? optional diode emulation and phase dropping ? pwm and analog track function ? forced pwm operation with negative current limiting and protection ? comprehensive fault protections ? selectable hiccup or latch-off fault response ? aec-q100 qualified, grade 1: -40c to +125c ? 5mmx5mm 32 ld wfqfn (wettable flank qfn) package applications ? automotive power system (e.g., 12v to 24v, 12v to 48v, etc.) - trunk audio amplifier - start-stop system - automotive boost applications ? industrial and telecommunication power supplies figure 1. simplified application schematic, 2-phase synchronous boost figure 2. efficiency curves, v in = 12v, t a = +25c isl78227 boot1 ph1 fb vout lg1 clkout pgood ug1 boot2 ph2 lg2 ug2 ss vin en track en_ic isen1n isen1p isen2n isen2p comp r sen1 r sen2 power-good clock_out pvcc vin vin pvcc pgnd pvcc 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 load current (a) v o = 18v v o = 36v v o = 24v efficiency (%) note: (see typical application in figure 4 on page 8 .) february 24, 2016 fn8808.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2015, 2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl78227 2 fn8808.2 february 24, 2016 submit document feedback table of contents functional pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical application - 2-phase synchronous boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 operation description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 synchronous boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pwm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 multiphase power conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 oscillator and synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 operation initialization and soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 pgood signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 current sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 adjustable slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 light-load efficiency enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 fault protections/indications and current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 internal 5.2v ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 output voltage setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 input inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 input capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 power mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 bootstrap capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 vcc input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 current sense circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
isl78227 3 fn8808.2 february 24, 2016 submit document feedback pin configuration isl78227 (32 ld 5x5 wfqfn) top view rdt atrk/dtrk isen2p isen2n isen1p isen1n vin boot1 fsync hic/latch de/phdrp rblank pllcomp en clkout boot2 vcc slope fb comp ss imon track pgood ug1 ph1 lg1 pvcc pgnd lg2 ph2 ug2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 sgnd functional pin description pin name pin # description vcc 1 ic bias power input pin for the internal analog circuitry. a minimum 1f ceramic capacitor should be used between vcc and ground for noise decoupling purposes. vcc is typically biased by pvcc or an external bias supply with voltage ranging from 4.75v to 5.5v. since pvcc is providing pulsing drive current, a small resistor like 10 or smaller between pvcc and vcc can help to filter out the noises from pvcc to vcc. slope 2 this pin programs the slope of the internal slope compen sation. a resistor should be connected from the slope pin to gnd. please refer to ? adjustable slope compensation ? on page 32 for how to select this resistor value. fb 3 the inverting input of the error amplifier for the voltage re gulation loop. a resistor network must be placed between the fb pin and the output rail to set the boost converter?s output voltage. please refer to ? output voltage setting ? on page 37 for more details. there are also output overvoltage and undervoltage comparators monitoring this pin. please refer to ? output overvoltage fault protection ? and ? output undervoltage indication ? on page 34 for more details. comp 4 the output of the transconductance error amplifier (gm1) for the output voltage regulation loop. place the compensation network between the comp pin and ground. please refer to ? output voltage regulation loop ? on page 25 for more details. the comp pin voltage can also be controlled by the constant current control loop error amplifier (gm2) output through a diode ( d cc ) when the constant current control loop is used to control the input average current. please refer to ? constant current control (cc) ? on page 35 for more details. ss 5 a capacitor placed from ss to ground will set up the soft-sta rt ramp rate and in turn determine the soft-start time. please refer to ? soft-start ? on page 30 for more details.
isl78227 4 fn8808.2 february 24, 2016 submit document feedback imon 6 imon is the average current monitor pin for the sum of the two phases? inductor cu rrents. it is used for average current l imiting and average current protection functions. the sourcing current from the imon pin is the sum of the two csa?s outputs plus a fixed 17a offset current. with each csa sensing individual phase?s inductor current, the imon signal represents the sum of th e two phases? inductor currents and it is the input current for the boost. a resistor in parallel with a capacitor are needed to be placed from imon to ground. the imon pin output current signal builds up the average voltage signal representing the average current sense signals. a constant average current limiting function and an average current protection are implemented based on the imon signal. 1. constant current control: a constant current (cc) control loop is implemented to control the imon average current signal equal to a 1.6v reference (vref_cc), which ultimate ly limits the total input average current to a constant level. 2. average current protection: if the imon pi n voltage is higher than 2v, the part will go into either hiccup or latch-off fault protection depending on the hic/latch pin configuration. refer to ? average current sense for 2 phases - imon ? on page 31 for more details. track 7 external reference input pin for the ic output voltage regu lation loop to follow. the inpu t reference signal can be eithe r digital or analog signal selected by the atrk/dtrk pin configuration. if the track function is not used, connect the track pin to vc c and the internal vref_1.6v will work as the reference. refer to ? digital/analog track function ? on page 25 for more details. pgood 8 provides an open-drain power-good signal. pull up this pin with a resistor to this ic?s vcc for proper function. when the output voltage is within ov/uv threshol ds and soft-start is completed, the internal pgood open-drain transistor is open and pgood is pulled high. it will be pulled low once output uv /ov or input ov conditions are detected. refer to ? pgood signal ? on page 30 for more details. fsync 9 a dual-function pin for switching frequency setting and synchronizatio n defined as follows:. 1. the pwm switching frequency can be programmed by a resistor r fsync from this pin to ground. the pwm frequency refers to a single-phase switching frequency in this da tasheet. the typical programmable frequency range is 50khz to 1.1mhz. 2. the pwm switching frequency can also be synchronized to an external clock applied on the fsync pin. the fsync pin detects the input clock signal?s rising edge that it is to be synchronized with. the typical detectable minimum pulse width of the input clock is 20ns. the rising edge of lg1 is delayed by 35ns from the rising edge of the input clock signal at the fsync pin. once the internal clock is locked to the external clock, it will latch to the external clock. if the external clock on the fsync pin is removed, the sw itching frequency oscillator will shut down. the part will then detect pll_lock fault and go to either hiccup mode or latch-off mode depending on the hic/latchoff pin configuration. if the part is set in hiccup mode , the part will restart with frequency set by r fsync . the typical synchronization frequency range is 50khz to 1.1mhz. the phase dropping mode is not allowed with external synchronization. refer to ? oscillator and synchronization ? on page 28 for more details. hic/latch 10 this pin is used to select either hiccup or latch-of f response to faults including output overvoltage (monitoring th e fb pin), output undervoltage (monitoring the fb pin, default inactive), v in overvoltage (monitoring the fb pin), peak overcurrent protection (oc2_peak), and average curr ent protection (monitoring the imon pin), etc. hic/latch = high to have hiccup fault response. hic/latch = low to have latch-off fault response. either togg ling the en pin or recycling vcc por resets the ic from latch-off status. refer to ? selectable hiccup or latch-off fault response ? on page 33 for more details. de/phdrp 11 this pin is used to select diode emulation mode (de), phase dropping (ph_drop) mode or continuous conduction mode (ccm). there are 3 configurable modes: 1. de mode; 2. de plus ph_drop mode; 3. ccm mode. refer to table 2 on page 33 for the 3 configurable options. the phase dropping mode is not allowed with external synchronization. rblank 12 a resistor from this pin to ground programs the blanking time for current-sensing after the pwm is on (lg is on). this blanking time is also termed as t minon time meaning minimum on-time once a pwm pulse is on. refer to ? minimum on-time (blank time) consideration ? on page 28 for the selection of r blank . pllcomp 13 this pin serves as the compensation node for the swit ching frequency clock?s pll (phase lock loop). a second order passive loop filter connected between this pin and ground compensates the pll loop. refer to ? oscillator and synchronization ? on page 28 for more details. en 14 this pin is a threshold-sensitive enable input for the cont roller. when the en pin is driven above 1.21v (typical), the isl78227 is enabled and the internal ldo is activated to po wer up pvcc followed by a start-up procedure. driving the en pin below 0.95v will disable the ic and clear all fault states. refer to ? enable ? on page 30 for more details. clkout 15 this pin outputs a clock signal with same frequency to on e phase?s switching frequency. the rising edge signal on the c lkout pin is delayed by 90 from the rising edge of lg1 of the same ic. with clkout connected to the fsync pin of the second isl78227, a 4-phase interleaving operation can be achieved. refer to ? oscillator and synchronization ? on page 28 for more details. functional pin description (continued) pin name pin # description
isl78227 5 fn8808.2 february 24, 2016 submit document feedback boot2 16 this pin provides bias voltage to the phase 2 high-side mo sfet driver. a bootstrap circuit is used to create a voltage s uitable to drive the external n-channel mosfet. a 0.47f ceramic capacitor in series with a 1.5 resistor are recommended between the boot2 and ph2 pins. in the typical configuration, pvcc is providing the bias to boot2 through a fast switching diode. in applications where a high-side driver is not needed (standard boost application for example), boot2 is recommended to be connected to ground. the isl78227 ic can detect boot 2 being grounded during start-up and both the phase 1 and phase 2 high-side drivers will be disabled. in additi on, ph1 and ph2 should al so be tied to ground. ug2 17 phase 2 high-side gate driver output. this output can be disabled by tying either boot1 and ph1 to ground or boot2 and ph2 to ground. ph2 18 connect this pin to the source of the phase 2 high-side mosfets and the dr ain of the low-side mosfets. this pin represents the return path for the phase 2 high-side gate drive. lg2 19 phase 2 low-side gate driver output. it should be connected to the phase 2 low-side mosfets? gates. pgnd 20 provides the return path for the low-side mosfet drivers. this pin carries a noisy drivin g current and traces connecting from this pin to the low-side mosfet source and pvcc decoup ling capacitor ground pad should be as short as possible. all the sensitive analog signal traces sh ould not share common traces with this dr iver return path. connect this pin to the ground copper plane (wiring away from the ic instead of connecting through the ic bottom pad) through several vias as close as possible to the ic. pvcc 21 output of the internal linear regulato r that provides bias for the low-side driver, high-side driver (pvcc connected to b ootx through diodes) and vcc bias (pvcc and vcc are ty pically connected through a small resistor like 10 or smaller, which helps to filter out the noises from pvcc to vcc). the pvcc operating range is 4.75v to 5.5v. a minimum 10f decoupling ceramic capacitor should be used between pvcc and pgnd. refer to ? internal 5.2v ldo ? on page 36 for more details. lg1 22 phase 1 low-side gate driver output. it should be connected to the phase 1 low-side mosfets? gates. ph1 23 connect this pin to the source of the phase 1 high-side mosfets and the dr ain of the low-side mosfets. this pin represents the return path for the phase 1 high-side gate drive. ug1 24 phase 1 high-side mosfet gate drive output. this output can be disabled by tying either boot1 and ph1 to ground or boot2 and ph2 to ground. boot1 25 this pin provides bias voltage to the phase 1 high-side mo sfet driver. a bootstrap circuit is used to create a voltage s uitable to drive the external n-channel mosfet. a 0.47f ceramic capacitor in series with a 1.5 resistor are recommended between boot1 and ph1 pins. in typical configura tion, pvcc is providing the bias to boot1 through a fast switching diode. in applications where a high-side driver is not needed (for example, standard boost application), the boot1 is recommended to be connected to ground. the isl78227 ic ca n detect boot1 being grounded during start-up and both the phase 1 and phase 2 high-side drivers will be disabled. in addition, ph1 and ph2 should also be tied to ground. vin 26 connect supply rail to this pin. typically, connect boost inpu t voltage to this pin. this pi n is connected to the input of the internal linear regulator, generating the power necessary to operate the chip. the dc voltage applied to vin should not exceed 55v during normal operation. vin can withstand transients up to 60v, but in this case, the device's overvoltage protection will sto p it from switching to pr otect itself. refer to ? input overvoltage fault protection ? on page 34 for more details. isen1n 27 the isen1n pin is the negative potential input to the phase 1 current sense amplifier. this amplifier continuously sens es the phase 1 inductor current through a powe r current sense resistor in series with the inductor. the sensed current signal is used for current mode control, peak current li miting, average current limiting and diode emulation. isen1p 28 the isen1p pin is the positive potentia l input to the phase 1 current sense amplifier. isen2n 29 the isen2n pin is the negative potential input to the ph ase 2 current sense amplifier. this amplifier continuously sens es the phase 2 inductor current through a powe r current sense resistor in series with the inductor. the sensed current signal is used for current mode control, peak current li miting, average current limiting and diode emulation. isen2p 30 the isen2p pin is the positive phase input to the phase 2 current sense amplifier. atrk/dtrk 31 the logic input pin to select the input signal format options for the track pin. pull this pin high for the track pi n to accept analog input signals. pull this pin low for th e track pin to accept digital input signals. refer to ? digital/analog track function ? on page 25 for more details. rdt 32 a resistor connected from this pin to ground programs the dead times between ugx off to lgx on and lgx off to ugx on to prevent shoot-through. please refer to ? driver configuration ? on page 24 for the selection of rdt. sgnd - signal ground bottom pad for the internal sensitive analog ci rcuits to be referred to, also serves as thermal pad. connect this pad to large ground plane. put multiple vias (as many as possible) in this pad connecting to the ground copper plane to help reduce the ic?s ? ja . in layout power flow planning, avoid having th e noisy high frequency pulse current flow through the sgnd area. functional pin description (continued) pin name pin # description
isl78227 6 fn8808.2 february 24, 2016 submit document feedback ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL78227ARZ isl7822 7arz -40 to +125 32 ld 5x5 wfqfn l32.5x5h isl78227ev1z evaluation board notes: 1. add ?-t? suffix for 6k unit or ?-t7a? suffix for 250 unit tape and reel options. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau-ag plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-fr ee products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl78227 . for more information on msl please see techbrief tb363 . table 1. key differences between family of parts part number topology pmbus? ntc track function package isl78229arz 2-phase boost controller yes yes yes 40 ld 6x6 wfqfn ISL78227ARZ 2-phase boost controller no no yes 32 ld 5x5 wfqfn
isl78227 7 fn8808.2 february 24, 2016 submit document feedback block diagram figure 3. block diagram 5.2v ldo vin pvcc vcc ss 1.2*vref_1.6v 0.8*vref_1.6v pgood gm1 atrk/dtrk vref_1.6v fb comp clkout pllcomp fsync slope r2 q s r1 csa isen1p isen1n boot1 ug1 ph1 lg1 de/phdrp duplicate for each phase i sen1 105a oc2_peak_ph1 i sen1 drop_phase2 sgnd (bottom pad) 5a fault fault logic pllcomp_short vout_ov pvcc pgnd pgnd oc_avg vref_trk de mode and phase drop mode selection imon 2v oc_avg gm2 programmable adaptive dead time rdt rblank hic/latch lp filter track vref_2.5v 1k m u x ss clock v ramp 80a oc1_ph1 -48a oc_neg_ph1 i sen1 i sen1 2a i sen1 vco pll clock slope compensation vin_ov oc2_peak_ph1 oc2_peak_ph2 atrak/ dtrk 48 por 1.21v en en en vin/48 otp pll soft-start delayand logic en_ss pwm control zcd_ph1 17a 3.47v vref_trk 0.3v ss hiccup /latchoff 1.1v phase_drop vref_cc(1.6v) 1.21v 112a 112a 8 8 iout v imon v fb v fb vin_ov fault initialization delay en_de phase drop control en_phase_drop hiccup retry delay latch-off logic ss_done en_hiccp en_latchoff i sen1 i sen2 (phase1) (phase2) pwm comparator cmp_pd cmp_ocavg d cc vout_ov vout_uv delay en pll_lock ? ? + + + - + - + - + - + -
isl78227 8 fn8808.2 february 24, 2016 submit document feedback typical application - 2- phase synchronous boost figure 4. typical application 2-phase synchronous boost isl78227 vcc boot1 ph1 fb vout lg1 clkout pgood ug1 boot2 ph2 pgnd lg2 ug2 vin ss vin pvcc en track vin en_ic isen1n isen1p isen2n isen2p imon de/phdrp hic/latch comp vcc rdt vcc rblank atrk/dtrk sgnd fsync slope pvcc_bt pllcomp pvcc vcc r blank r dt r pll c pll1 c pll2 r slope c ss r fb2 r fb1 r cp c cp1 c cp2 c imon r imon r bias1b r set1b r bias1a r set1a c isen1 l1 l2 r sen1 r sen2 c pvcc c vcc r vcc r fs c boot1 c boot2 d boot2 d boot1 c in c in c out c out r bias2b r set2b r bias2a r set2a c isen2 power-good r pg q1 q2 q3 q4 atrk/dtrk: = vcc to track analog signal = gnd to track digital signal hic/latch: = vcc for hiccup mode = gnd for latchoff mode de/phdrp: = vcc for de mode = float for de and phase-drop mode = gnd for ccm mode clock_out 10f 0.47f 0.47f pvcc_bt r pvccbt 5.1 1f 6.8nf 1nf 3.3k 10 1m 1m 220pf 220pf q1, q2, q3, q4: 2 buk9y6r0-60e in parallel ?? ?? ?? ?? ?? vcc
isl78227 9 fn8808.2 february 24, 2016 submit document feedback absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v ph1, ph2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v boot1, boot2, ug1, ug2 . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +65.0v upper driver supply voltage, v bootx - v phx . . . . . . . . . . . . - 0.3v to +6.5v pvcc, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +6.5v isen1p, isen1n, isen2p, isen2n . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v v isenxp - v isenxn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to vcc + 0.3v esd rating human body model (tested per aec-q100-002) . . . . . . . . . . . . . . . . 2kv charged device model (tested per aec-q100-011). . . . . . . . . . . . . 750v latch-up rating (tested per aec-q100-004) . . . . . . . . . . . . . . . . . . 100ma thermal resistance ? ja (c/w) ? jc (c/w) 32 ld 5x5 wfqfn package ( notes 4 , 5 ). . . 30 1.2 maximum junction temperature (plastic package) . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v to +55v pvcc, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75v to 5.5v ph1, ph2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +55v upper driver supply voltage, v bootx - v phx . . . . . . . . . . . . . . . . 3.5v to 6v isen1p to isen1n and isen2p to isen 2n differential voltage . . . . 0.3v isen1p, isen1n, isen2p, isen2n commo n-mode voltage . . . . 4v to 55v operational junction temperature rang e (automotive) . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, t a = -40c to +125c ( note 7 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit supply input input voltage range v in switching, under the condition of internal ldo having dropout (v in - pvcc) less than 0.25v 555 v input supply current to the vin pin (ic enabled) i q_sw en = 5v, vin = 12v, pvcc = vcc, boot1 and boot2 supplied by pvcc, r fsync = 40.2k (f sw = 300khz), lgx = open, ugx = open 8.0 10.0 ma i q_non-sw en = 5v, vin = 12v, pvcc = vcc, boot1 and boot2 supplied by pvcc, non-switching, lgx = open, ugx = open 6.0 8.5 ma input supply current to the vin pin (ic shutdown) i _sd_vin_55v en = gnd, vin = 55v 0.2 1.0 a input bias current (ic shutdown) to each of isen1p/isen1n/isen2p/isen2n pins i _sd_isenxp/n en = gnd, vin = 55v isen1p (or isen1n/isen2p/isen2n) = 55v -1 0 1 a input overvoltage protection vin ovp rising threshold (swi tching disable) en = 5v, v in rising 56.5 58.0 59.5 v vin ovp trip delay en = 5v, v in rising 5 s internal linear regulator ldo voltage (pvcc pin) v pvcc v in = 6v to 55v, c pvcc = 4.7f, i pvcc =10ma 5.0 5.2 5.4 v ldo saturation dropout voltage (pvcc pin) v dropout v in = 4.9v, c pvcc = 4.7f, i_pvcc = 80ma 0.3 v ldo current limit (pvcc pin) i oc_ldo v in = 6v, v pvcc = 4.5v 130 195 250 ma ldo output short current limit (pvcc pin) i ocfb_ldo v in = 6v, v pvcc = 0v 50 100 160 ma
isl78227 10 fn8808.2 february 24, 2016 submit document feedback power-on reset (for both pvcc and vcc) rising v vcc por threshold v porh_vcc 4.35 4.50 4.75 v falling v vcc por threshold v porl_vcc 4.05 4.15 4.25 v v vcc por hysteresis v porhys_vcc 0.4 v rising v pvcc por threshold v porh_pvcc 4.35 4.50 4.75 v falling v pvcc por threshold v porl_pvcc 3.0 3.2 3.4 v v pvcc por hysteresis v porhys_pvcc 1.3 v soft-start delay t ss_dly from por rising to initiation of soft-start. r fsync = 61.9k, f sw = 200khz, pllcomp pin network of r pll = 3.24k, c pll1 = 6.8nf and c pll2 = 1nf 0.85 ms en enable threshold v enh en rising 1.13 1.21 1.33 v v enl en falling 0.85 0.95 1.10 v v en_hys hysteresis 250 mv input impedance en = 4v 2 6m pwm switching frequency pwm switching frequency (per phase) f osc r fsync = 249k (0.1%) 46.0 50.2 54.5 khz r fsync = 82.5k (0.1%) 142 150 156 khz r fsync = 40.2k (0.1%) 290 300 310 khz r fsync = 10k (0.1%) 990 1100 1170 khz minimum adjustable switching frequency 50 khz maximum adjustable switching frequency 1100 khz fsync pin voltage 0.5 v minimum on-time (blanking time) on lgx t minon_1 minimum duty cycle, c ug = c lg = open r blank = 80k (0.1%) 315 410 525 ns t minon_2 minimum duty cycle, c ug = c lg = open r blank = 50k (0.1%) 175 260 325 ns t minon_3 minimum duty cycle, c ug = c lg = open r blank = 25k (0.1%) 100 140 180 ns t minon_4 minimum duty cycle, c ug = c lg = open r blank = 10k 75 90 105 ns maximum duty cycle d max d max = t_lg_ on/t sw , v comp = 3.5v, f sw = 300khz, rdt = 18.2k , c ug =open, c lg = open 88.5 89.0 90.5 % synchronization (fsync pin) minimum synchronization frequency at fsync input 50 khz maximum synchronization frequency at fsync input 1100 khz input high threshold vih 3.5 v input low threshold vil 1.5 v input minimum pulse width - rise-to-fall 20 ns electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, t a = -40c to +125c ( note 7 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl78227 11 fn8808.2 february 24, 2016 submit document feedback input minimum pulse width - fall-to-rise 20 ns delay time from input pulse rising to lg1 rising edge minus dead time t dt1 c lg = open, rdt = 50k 35 ns input impedance input impedance before synchronization mode 1k input impedance after synchronization mode 200 m clkout clkout h i clkout = 500a vcc - 0.5 vcc - 0.1 v clkout l i clkout = -500a 0.1 0.4 v output pulse width c clkout = 100pf, t sw is each phase?s switching period 1/12 * t sw phase shift from lg1 rising edge to clkout pulse rising edge c lg1 = open, c clkout = open, f sw = 300khz, t dt1 = 60ns (please refer to figure 56 on page 28 for the timing diagram) 87 soft-start soft-start current i ss 4.5 5.0 5.5 a minimum soft-start prebias voltage 0v maximum soft-start prebias voltage 1.6 v soft-start prebias voltage accuracy v fb = 500mv -25 0 25 mv soft-start clamp voltage v ssclamp 3.25 3.47 3.70 v hiccup retry delay ( please refer to ? selectable hiccup or latch-off fault response ? on page 33 for details ) hiccup retry delay if hiccup fault response selected 500 ms reference voltage for output voltage regulation system reference accuracy measured at the fb pin 1.576 1.600 1.620 v fb pin input bias current v fb = 1.6v, track = open -0.05 0.01 0.05 a error amplifier for output voltage regulation (gm1) transconductance gain 2ma/v output impedance 7.5 m unity gain bandwidth c comp = 100pf from comp pin to gnd 3.3 mhz slew rate c comp = 100pf from comp pin to gnd 3 v/s output current capability 300 a maximum output voltage 3.5 3.7 v minimum output voltage 0.1 0.3 v pwm core slope pin voltage 480 500 520 mv slope accuracy r slope = 20k (0.1%) -20 0 20 % r slope = 40.2k (0.1%) -20 3 20 % duty cycle matching v rsenx = 30mv, r setx = 665 (0.1%), r slope = 27k, f sw = 150khz, v comp = 2.52v, measure (t on_lg2 - t on_lg1 )/(t on_lg2 + t on_lg1 ) *2 3% electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, t a = -40c to +125c ( note 7 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl78227 12 fn8808.2 february 24, 2016 submit document feedback current sense amplifier minimum isenxn and isenxp common-mode voltage range accuracy becomes worse when lower than 4v 4v maximum isenxn and isenxp common-mode voltage range 55 v maximum input differential voltage range v isenxp - v isenxn 0.3 v isenxp/isenxn bias current i senxp/n_bias sourcing out of pin, en = 5v, v isenxn =v isenxp , v cm = 4v to 55v 100 123 150 a zcd detection - csa zero crossing detection (zcd) threshold v zcd_csa measures voltage threshold before r sen at csa inputs (equivalent to the voltage across the current sense shunt resistor), r set = 665 (0.1%) -4.0 1.3 6.0 mv phase dropping v imon phase-drop falling threshold, to drop phase 2 v phdrp_th_f when v imon falls below v phdrp_th_f , drop off phase 2 1.0 1.1 1.2 v v imon phase-add rising threshold, to add phase 2 v phadd_th_r when v imon rise above v phadd_th_r , add back phase 2 1.05 1.15 1.25 v v imon phase-drop thre shold hysteresis v phdrp_hys when v imon isl78227 13 fn8808.2 february 24, 2016 submit document feedback average constant current control loop imon current accuracy v rsenx = 30mv, r setx = 665 (0.1%), with isenxp/n pins biased at 4v or 55v common-mode voltage 27.0 28.3 29.5 a imon offset current v rsenx = 0v, r set = 665 (0.1%), with isenxp/n pins biased at 4v or 55v common-mode voltage 16 17 18 a constant current control reference accuracy vref cc measure the imon pin 1.575 1.600 1.625 v average overcurrent fault protection oc_avg, ( refer to ? average overcurrent fault (oc_avg) protection ? on page 36 for details ) oc_avg fault threshold at the imon pin 1.9 2.0 2.1 v oc_avg fault trip delay 1s gate drivers ug source resistance r ug_source 100ma source current, v boot - v ph = 4.4v 1.2 ug source current i ug_source v ug - v ph = 2.5v, v boot - v ph = 4.4v 2 a ug sink resistance r ug_sink 100ma sink current, v boot - v ph = 4.4v 0.6 ug sink current i ug_sink v ug - v ph = 2.5v, v boot - v ph = 4.4v 2.0 a lg source resistance r lg_source 100ma source current, pvcc = 5.2v 1.2 lg source current i lg_source v lg - pgnd = 2.5v, pvcc = 5.2v 2.0 a lg sink resistance r lg_sink 100ma sink current, pvcc = 5.2v 0.55 lg sink current i lg_sink v lg - pgnd = 2.5v, pvcc = 5.2v 3 a ug to ph internal resistor 50 k lg to pgnd internal resistor 50 k boot-ph uvlo detection threshold 2.8 3.0 3.2 v boot-ph uvlo detection threshold hysteresis 0.09 0.15 0.22 v dead time delay - ug falling to lg rising t dt1 c ug = c lg = open, r dt = 10k (0.1%) 55 70 85 ns dead time delay - lg falling to ug rising t dt2 c ug = c lg = open, r dt = 10k (0.1%) 65 80 95 ns dead time delay - ug falling to lg rising t dt1 c ug = c lg = open, r dt = 18.2k (0.1%) 85 100 115 ns dead time delay - lg falling to ug rising t dt2 c ug = c lg = open, r dt = 18.2k (0.1%) 95 110 125 ns dead time delay - ug falling to lg rising t dt1 c ug = c lg = open, r dt = 50k (0.1%) 185 210 240 ns dead time delay - lg falling to ug rising t dt2 c ug = c lg = open, r dt = 50k (0.1%) 205 230 260 ns dead time delay - ug falling to lg rising t dt1 c ug = c lg = open, r dt = 64.9k (0.1%) 235 265 295 ns dead time delay - lg falling to ug rising t dt2 c ug = c lg = open, r dt = 64.9k (0.1%) 260 290 320 ns output overvoltage detection/protection monitor the fb pin , (refer to ? output overvoltage fault protection ? on page 34 for details) fb overvoltage rising trip threshold v fbov_rise percentage of vref_1.6v (selectable hiccup/latch-off response) 118 120 122 % fb overvoltage falling recovery threshold v fbov_fall percentage of vref_1.6v (selectable hiccup/latch-off response) 114 116 118 % overvoltage threshold hysteresis 4% fb overvoltage trip delay 1s electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, t a = -40c to +125c ( note 7 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl78227 14 fn8808.2 february 24, 2016 submit document feedback output undervoltage detection (monitor the fb pin , (refer to ? output undervoltage indication ? on page 34 for details ) undervoltage falling trip threshold v fbuvref_fall percentage of vref_1.6v 78 80 82 % undervoltage rising recovery threshold v fbuvref_rise percentage of vref_1.6v 82.5 84.0 86.5 % undervoltage threshold hysteresis 4% power-good monitor (pgood pin) pgood leakage current pgood high, v pgood = 5v 1 a pgood low voltage pgood low, i pgood = 0.5ma 0.06 0.40 v pgood rising delay (de mode) the pgood rising delay from v sspin =v sspclamp (3.47v) and vref_trk 0.3v to pgood high when de mode is selected (de/phdrp = vcc or float) 0.5 ms pgood rising delay (ccm mode) t he pgood rising delay from v sspin =v sspclamp (3.47v) and vref_trk 0.3v to pgood high when ccm mode is selected (de/phdrp = gnd) 100 ms pgood falling blanking time 10 s hic/latch, atrk/dtrk pin digital logic input input leakage current en <1v -1 1 a input pull down current en >2v, pin voltage = 2.1v 0.7 1.0 2.0 a logic input low 0.8 v logic input high 2.1 v de/phdrp pin digital logic input (high/low/float) input leakage current -1 1 a float impedance - pin to vcc pin = gnd 100 200 300 k float impedance - pin to gnd pin = vcc 100 200 300 k output voltage on float pin pin = float 2.1 2.6 2.7 v tri-state input voltage max 3v tri-state input voltage min 1.8 v logic input low pin voltage falling 0.7 v logic input high pin voltage rising vcc - 0.4 v track pin - digital input logic input leakage current en <1v, pin voltage = 5v, v cc = 0v -1 1 a input pull-up current en >2v, pin voltage = 0v, v cc = 5v 0.8 1.1 1.5 a input pull-up current compliance voltage en >2v, pin open 2.5 v logic input low pin voltage falling 0.8 v logic input high pin voltage rising 2 v electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, t a = -40c to +125c ( note 7 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl78227 15 fn8808.2 february 24, 2016 submit document feedback duty cycle conversion (fb accuracy) 0% duty cycle input, measure at the fb pin 0 v 25% duty cycle input, frequency = 400khz, measure at the fb pin 0.600 0.625 0.650 v 50% duty cycle input, frequency = 400khz, measure at the fb pin 1.218 1.253 1.288 v 60% duty cycle input, measure at the fb pin 1.45 1.49 1.53 v track pin - analog input input leakage current v track = 1.6v, leakage current into this pin to ground -1.0 -0.6 -0.3 a track input reference voltage range 0 1.6 v track input reference voltage accuracy measure at the fb pin, v track = 1.5v -4.0 -0.5 4.0 % measure at the fb pin, v track = 0.5v -6.0 1.8 6.0 % track ss_done detection threshold 0.29 0.30 0.31 v over-temperature protection over-temperature trip point 160 c over-temperature recovery threshold 145 c notes: 6. compliance to datasheet limits are assu red by one or more methods: production test, characterization and/or design. 7. the ic is tested in conditions with mini mum power dissipations in the ic meaning t a t j . electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, t a = -40c to +125c ( note 7 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl78227 16 fn8808.2 february 24, 2016 submit document feedback performance curves unless otherwise specified, operating cond itions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. figure 5. efficiency vs load, 2-phase boost, 3 modes operation, f sw = 200khz, v in = 12v, v out = 36v, t a = +25c figure 6. en into preb iased output, ccm mode (de/phdrp = gnd), i out = 0a figure 7. en on and initialization to start-up, i out = 0a figure 8. soft-start, ccm mode (de/phdrp = gnd), i out =8a figure 9. en on and initialization to start-up, i out = 0a figure 10. soft-start, de+phdrop mode (de/phdrp = float), i out = 8a note: (see typical application in figure 4 on page 8 .) 50 55 60 65 70 75 80 85 90 95 100 0.01 0.10 1.00 10.00 100.00 load current (a) de with phase drop de without phase drop ccm efficiency (%) ss 3.0v/div i l1 5.0a/div v out 1.0v/div with 36v offset ph1 30.0v/div 10ms/div pllcomp 500mv/div pvcc 2.0v/div ss 700mv/div ph1 30.0v/div 500s/div 20ms/div ss 3.0v/div pgood 5.0v/div v out 20.0v/div ph1 30.0v/div clkout 5.0v/div pvcc 2.0v/div pllcomp 500mv/div ss 2.0v/div 200s/div ss 3.0v/div pgood 5.0v/div v out 20.0v/div ph1 30.0v/div 5ms/div
isl78227 17 fn8808.2 february 24, 2016 submit document feedback figure 11. soft-start, de mode (de/phdrp = vcc), i out = 8a figure 12. en shutdown, pvcc/pgood/ss fall, i out = 0a figure 13. en shutdown, i out = 8a figure 14. ccm mode (de/ph drp = gnd), phase 1 inductor ripple current, i out = 0a figure 15. en shutdown, i out = 8a figure 16. ccm mode (de/ph drp = gnd), phase 2 inductor ripple current, i out = 0a performance curves unless otherwise specified, operating cond itions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) ss 3.0v/div pgood 5.0v/div v out 20.0v/div ph1 30.0v/div 5ms/div pvcc 2.0v/div pgood 3.0v/div ss 2.0v/div ph1 30.0v/div 20ms/div pgood 5.0v/div ph2 40.0v/div ph1 40.0v/div 20s/div v out 20.0v/div lg1 5.0v/div i l1 4.0a/div v out 30.0v/div 10s/div lg2 5.0v/div v out 20.0v/div pgood 4.0v/div ph2 30.0v/div ph1 30.0v/div 5ms/div lg1 5.0v/div i l2 4.0a/div v out 30.0v/div 10s/div lg2 5.0v/div
isl78227 18 fn8808.2 february 24, 2016 submit document feedback figure 17. de mode (de/phdr p = vcc), diode emulation operation, pulse skipping, i out = 0a figure 18. de mode (de/phdr p = vcc), diode emulation operation, i out = 29ma figure 19. de mode (de/phdrp = vcc), ph1 and ph2 diode emulation operation, pulse skipping, i out = 7ma figure 20. de+ph_drop mode (de/phdrp = float), ph1 diode emulation with ph2 dropped, i out = 29ma figure 21. de+phdrp mode (de/phdrp = float), ph1 diode emulation with ph2 dropped, i out = 7ma figure 22. de+phdrp mode (de/phdrp = float), ph2 added and dropped, under transient step load of 1a to 8a performance curves unless otherwise specified, operating cond itions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) v out 1.0v/div with 36v offset pgood 4.0v/div ph1 20.0v/div 5s/div ph2 20.0v/div ph2 30.0v/div ph1 30.0v/div 2s/div v out 10.0v/div ph2 30.0v/div ph1 30.0v/div 10s/div v out 10.0v/div ph1 30.0v/div ph2 30.0v/div 2s/div v out 10.0v/div ph1 30.0v/div ph2 30.0v/div 10s/div v out 10.0v/div ph2 30.0v/div ph1 30.0v/div 10ms/div imon 300mv/div i_load 5.0a/div
isl78227 19 fn8808.2 february 24, 2016 submit document feedback figure 23. analog tracking 10 0hz sinusoidal signal, ccm mode (de/phdrp = gnd), atrk/dtrak = vcc, i out = 1a figure 24. analog tracking 300hz sinusoidal signal at the track pin, ccm mode (de/phdrp = gnd), atrk/dtrak = vcc, i out = 1a figure 25. steady-state operation of input constant current mode, i in controlled at 43a constant, v out = 19.5v figure 26. digital tracking (tracking signal, frequency = 400khz, d = 0.5, v out = 28.3v figure 27. load current keep in creasing from no load to overload (25a), v out starts to drop when input constant current mode starts to work, input current is finally controlled to be constant figure 28. digital tracking (tracking signal, frequency = 400khz, d = 0.3), v out = 17v performance curves unless otherwise specified, operating cond itions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) fb 300mv/div track 300mv/div v out 6.8v/div ph1 20.0v/div 2ms/div fb 300mv/div track 300mv/div v out 6.8v/div ph1 20.0v/div 2ms/div v out 30.0v/div i_in 16a/div imon 500mv/div ph1 30.0v/div 50s/div v out 7.0v/div track 4.0v/div ph2 40.0v/div ph1 40.0v/div 1s/div v out 30.0v/div i_in 16a/div imon 500mv/div ph1 30.0v/div 1s/div v out 7.0v/div track 4.0v/div ph2 40.0v/div ph1 40.0v/div 1s/div
isl78227 20 fn8808.2 february 24, 2016 submit document feedback figure 29. digital tracking, (tracking signal, frequency = 200khz, d = 0.5), v out = 28.3v figure 30. de mode (de/phdrp = vcc), transient response, i out = 0.03a to 8a step load figure 31. ccm mode (de/phdrp = gnd), transient response, i out = 0a to 8a step load figure 32. de+ph_drop mode (de/phdrp = float), transient response, i out = 1a to 8a step load figure 33. shutdown current at the vin pin i_sd vs temperature, v in = 55v figure 34. ic operational quiescent current vs temperature, ic switchin g, no load on lgx and ugx performance curves unless otherwise specified, operating cond itions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) v out 1.0v/div with 28v offset track 4.0v/div ph2 40.0v/div ph1 40.0v/div 10s/div ph2 30.0v/div i_load 5.0a/div v out 2.0v/div with 36v offset ph1 30.0v/div 10ms/div ph2 30.0v/div i_load 5.0a/div v out 1.0v/div with 36v offset ph1 30.0v/div 1ms/div ph2 30.0v/div i_load 5.0a/div v out 1.0v/div with 36v offset ph1 30.0v/div 5ms/div 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 150 temperature (c) i_sd_vin (a) 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 temperature (c) iq_sw (ma)
isl78227 21 fn8808.2 february 24, 2016 submit document feedback figure 35. ic operationa l quiescent current vs temperature, ic not switching figure 36. v ref_cc system accuracy vs temperature, measured at the imon pin, vref_cc = 1.6v figure 37. imon output current accuracy (current-sensing signal output) vs temperature, v rsenx = 30mv, r setx = 665 ? (0.1%) figure 38. vref_1.6v system accuracy vs temperature, measured at the fb pin figure 39. internal ldo dropout voltage vs temperature, 80ma load current on ldo output (pvcc) figure 40. internal ldo overcurrent threshold and its foldback overcurrent threshold vs temperature performance curves unless otherwise specified, operating cond itions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 temperature (c) iq_non-sw (ma) 1.590 1.591 1.592 1.593 1.594 1.595 1.596 1.597 1.598 1.599 1.600 1.601 1.602 1.603 1.604 1.605 1.606 1.607 1.608 1.609 1.610 -50 -25 0 25 50 75 100 125 150 temperature (c) v ref_cc system accuracy (v) 26.0 26.5 27.0 27.5 28.0 28.5 29.0 -50 -25 0 25 50 75 100 125 150 temperature (c) v in = 55v v in = 4v imon current (a) 1.590 1.591 1.592 1.593 1.594 1.595 1.596 1.597 1.598 1.599 1.600 1.601 1.602 1.603 1.604 1.605 1.606 1.607 1.608 1.609 1.610 -50 -25 0 25 50 75 100 125 150 temperature (c) vref_1.6v system accuracy (v) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 150 temper atu r e ( c ) vdropout_ldo (v) 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 -50 -25 0 25 50 75 100 125 150 temperature (c) ioc_ldo (ma) iocfb_ld o (ma) iocfb_ldo, ioc_ldo (mv)
isl78227 22 fn8808.2 february 24, 2016 submit document feedback figure 41. v in ov rising threshold vs temperature figure 42. pvcc/vcc por rising threshold vs temperature figure 43. oc1 voltage threshold (across rsen) vs temperature figure 44. pvcc/vcc por falling threshold vs temperature figure 45. analog tracking reference system accuracy vs temperature, measured at the fb pin, v track =0.5v figure 46. analog tracking reference system accuracy vs temperature, measur ed at the fb pin, v track = 1.5v performance curves unless otherwise specified, operating cond itions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) 55 56 57 58 59 60 -50 -25 0 25 50 75 100 125 150 temperature (c) vin_ov_rise (v) 4.2 4.3 4.4 4.5 4.6 -50 -25 0 25 50 75 100 125 150 temperature (c) vpor h_vcc (v) vporh_pvcc (v) vporh_pvcc, vporh_vcc (v) 30 35 40 45 50 55 60 -50-25 0 25 50 75100125150 temperature (c) voc1 (mv) 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 -50 -25 0 25 50 75 100 125 150 temperature (c) vporl_vcc (v) vporl_pvcc (v) vporl_pvcc, vporl_vcc (v) 0.5 0.7 0.9 1.1 1.3 1.5 -50 -25 0 25 50 75 1 00 125 150 temperature (c) analog track reference systeme accuracy_0.5v (%) -3 -2 -1 0 1 2 3 -50 -25 0 25 50 75 100 125 150 temperature (c) analog track reference system accuracy_1.5v (%)
isl78227 23 fn8808.2 february 24, 2016 submit document feedback figure 47. digital tracking reference system accuracy vs temperature, measured at the fb pin, duty cycle of track pin signal is 0.5 figure 48. gate drive dead time vs temperature, r dt = 10k, t dt1 refers to ug falling to lg rising, t dt2 refers to lg falling to ug rising figure 49. gate drive dead time vs temperature, r dt = 18.2k, t dt1 refers to ug falling to lg rising, t dt2 refers to lg falling to ug rising performance curves unless otherwise specified, operating cond itions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) 1.245 1.247 1.249 1.251 1.253 1.255 1.257 1.259 1.261 1.263 1.265 -50 -25 0 25 50 75 100 125 150 temperature (c) digital track reference system accuracy (v) 0 10 20 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 150 temperature (c) t dt 2 t dt 1 dead time (ns) 50 60 70 80 90 100 110 120 130 140 150 -50 -25 0 25 50 75 100 125 150 temperature (c) t dt 1 t dt 2 dead time (ns)
isl78227 24 fn8808.2 february 24, 2016 submit document feedback operation description the isl78227 is a 2-phase synchronous boost controller with integrated drivers. it supports wide input and output ranges of 5v to 55v during normal operatio n and the vin pin withstands transients up to 60v. the isl78227 is integrated with 2a sourcing/3a sinking strong drivers to support high efficiency and high current synchronous boost applications. the drivers have a unique feature of adaptive dead time control of which the dead time can be programmed for different external mosfets, achieving both optimized efficiency and reliable mosfet driving. the isl78227 has selectable diode emulation and phase dropping functions for enhanced light-load efficiency. the pwm modulation method is a constant frequency peak current mode control (pcmc), which have benefits of input voltage feed-forward, a simpler loop to compensate compared to voltage mode control and inherent current sharing capability. the isl78227 offers a track function with unique features of accepting either digital or analog signals for the user to adjust reference voltage externally. the digital signal track function greatly reduces the complexity of the interface circuits between the central control unit and the boost regulator. equipped with cycle-by-cycle positive and nega tive current limiting, the track function can be reliably facilitated to achieve an envelope tracking feature in audio ampl ifier applications, which can significantly improve system efficiency. in addition to the cycle-by-cycle current limiting , the isl78227 is implemented with a dedicated average constant current (cc) control loop for input current. for devices having only peak current limiting, the average current under peak current limiting varies quite largely because the inductor ripple varies with changes of v in and v out and tolerances of f sw and inductors. the isl78227?s unique cc control feature is able to have the average input current accurately controlled to be constant without shutdown. under certain constant input voltage, this means constant power limiting, which is especially useful for the boost converter. it helps the user optimize the system with the power devices? capability fully util ized by well controlled constant input power. details of the functions are desc ribed in the following sections. synchronous boost in order to improve efficiency, the isl78227 employs synchronous boost architecture as shown in figure 4 on page 8 . the ugx output drives the high-side synchronous mosfet, which replaces the freewheeling diode and reduces the power losses due to the voltage drop of the freewheeling diode. while the boost converter is operat ing in steady state continuous conduction mode (ccm), with each phase?s low-side mosfet controlled to turn on with duty cycle d and ideally the upper mosfet will be on for (1-d). equation 1 shows the input to output voltage dc transfer function for boost is: driver configuration as shown in figure 4 on page 8 , the upper side ugx drivers are biased by the c bootx voltage between bootx and phx (where ?x? indicates the specific phase nu mber and same note applied throughout this document) . c bootx is charged by a charge pump mechanism. pvcc charges bootx through the schottky diode d bootx when lgx is high pulling phx low. bootx rises with phx and maintains the voltage to drive ugx as the d bootx is reverse biased. at start-up, the charging to c bootx from 0 to ~4.5v will cause pvcc to dip a little. so a typical 5.1 resistor r pvccbt is recommended between pvcc and d bootx to prevent pvcc from falling below vporl_pvcc. the typical value for c bootx is 0.47f. the bootx to phx voltage is monitored by uvlo circuits. when bootx to phx falls below a 3v threshold, the ugx output is disabled. when bootx to phx rises back to be above this threshold plus 150mv hysteresis, the high-side driver output is enabled. for standard boost ap plication when upper side drivers are not needed, both ug1 and ug2 can be disabled by connecting either boot1 or boot2 to ground before part start-up initialization. phx should be connected to ground. programmable adaptive dead time control the ugx and lgx drivers are design ed to have an adaptive dead time algorithm that optimizes operation with varying operating conditions. in this algorithm, the device detects the off timing of lgx (ugx) voltages before turning on ugx (lgx). in addition to the adaptive dead time control, the dead time between ugx on and lgx on can be programmed by the resistor at the rdt pin. the typical range of programmable dead time is 55ns to 200ns, or larger. this is intended for different external mosfets applications to adjust the dead time, maximizing the efficiency while at the same time preventing shoot-through. refer to figure 50 on page 25 for the selection of the rdt resistor and dead time, where t dt1 refers to the dead time between ug falling to lg rising, and t dt2 refers to the dead time between lg falling to ug rising. the dead time is smaller with a lower value rdt resistor, and it?s clamped to minimum 57ns when rdt is shorted to ground. since a current as large as 4ma will be pulled from the rdt pin if the rdt pin is shorted to ground, it is recommended to use 5k as the smallest value for the rdt resistor where the current drawing from the rdt pin is 0.5v/5k = 100a. v out v in 1d C ------------- = (eq. 1)
isl78227 25 fn8808.2 february 24, 2016 submit document feedback pwm control the isl78227 uses fixed frequency peak current mode control architecture. as shown in figure 3 on page 7 and the typical schematic diagram, error amplifier (gm1) compares the fb pin voltage and reference voltage and generates a voltage loop error signal at the comp pin. this er ror signal is compared with the current ramp signal (vramp) by the pwm comparator. the pwm comparator output combined with fixed frequency clock signal controls the sr flip-flop to generate the pwm signals (refer to ? peak current mode control ? on page 26 ). output voltage regulation loop the resistor divider r fb2 and r fb1 from v out to fb ( figure 4 on page 8 ) can be selected to set the desired v out . v out can be calculated by equation 2 . where in normal operation after soft-start, v ref can be either vref_1.6v or vref_trk whichever is lower. there are 3 inputs for the reference voltage for gm1: soft-start ramp ss, vref_trk and vref_1.6v. the gm1 uses the lowest value among ss, vref_trk and vref_1.6v. ss, vref_trk and vref_1.6v are valid for gm1 during and after soft-start. in general application, vref_trk is normally high before soft-start and ss normally ramps up from a voltage lower than vref_trk and vref_1.6v, in which case ss controls the output voltage ramp-up during soft-start. after soft-start is complete, the user can adjust vref_trk for the desi red voltage. since vref_trk is valid before soft-start, to set vref_trk to be lower than ss can make the ss ramp ineffective since gm1 uses the lower vref_trk voltage. in such a case, the vref_trk becomes the real soft-start ramp that controls the output voltage ramp-up. digital/analog track function the track input provides an exte rnal reference voltage to be applied for the output voltage loop to follow, which is useful if the user wants to change the output voltage as required. an example is to employ envelope tracking technology in audio power amplifier applications. the isl78227 boost stage output is powering the audio power amplifier stage input, where the boost output tracks the music envelope signal applied at the track pin. ultimately, higher system efficiency can be achieved. the track pin can accept either a digital signal or an analog signal by configuring the atrk /dtrk pin to be connected to ground or vcc. figure 51 on page 26 shows the track function block diagram. vref_trk is fed into gm1 as one of the reference voltages. the gm1 takes the lowest voltage of ss, vref_trk and vref_1.6v as the actual reference. when vref_trk is the lowest voltage, it becomes the actual reference voltage for gm1 and the output voltage can be adjusted with track signal changes. regarding the effective vref_trk range: ? there is no limit for the minimum voltage on the track pin, but note the lower reference voltage and the lower voltage feedback regulation accuracy. note the ss_done signal is checking vref_trk 0.3v as one of the conditions (refer to figure 58 on page 29 and t 8 -t 9 description on page 30 ). also, for the boost converter, the re gulated output minimum voltage is usually the input voltage minus the upper mosfet?s body diode drop, in which case, the corresponding voltage at fb voltage is the minimum effective voltage for the vref_trk. ? the gm1 takes the lowest voltage of ss, vref_trk and vref_1.6v as the actual reference. the maximum effective range for vref_trk is determined by vref_1.6v or ss signal, whichever is lower. for example, after soft-start, when the ss pin equals to 3.47v (typical), the maximum effective voltage for vref_trk is 1.6v (vref_1.6v). when atrk/dtrk = gnd (dtrk mode), the track pin accepts digital signal inputs. vref_trk (as one of the references input for the error amplifier gm1) equals to the average duty cycle value of the pwm signal?s at the track pin. as shown in figure 51 on page 26 , the mux is controlled by the atrk/dtrk pin configurations. when atrk/dtrk = gnd, the mux connects the output of the q1 and q2 switch bridge to the input of a 2-stage rc filter (r 1 , c 1 , r 2 and c 2 ). the pwm signal at the track pin controls q1 and q2 to chop the 2.5v internal reference voltage. the phase node of q1 and q2 is a pwm signal with accurate 2.5v amplitude an d duty cycle d, where d is the input pwm duty cycle on the track input pin. the rc filter smooths out the pwm ac components and the voltage vref_trk after the rc filter becomes a dc voltage equal to 2.5v*d: according to equation 3 , the pwm signals? am plitude at the track pin doesn?t affect the vref_trk accuracy and only the duty cycle value changes the vref_trk value. in general, the vref_trk reference accuracy is as good as the 2.5v reference. the built-in low pass filter (r 1 , c 1 , r 2 and c 2 ) converts the pwm signal?s duty cycle value to a low noise reference. the low pass filter has cutoff frequency of 1.75khz and a gain of -40db at 400khz. the 2.5v figure 50. dead time vs rdt, t dt1 refers to ug falling to lg rising, t dt2 refers to lg falling to ug rising 0 50 100 150 200 250 300 5 10152025303540455055606570 rd t (k ? ) t dt 2 t dt 1 dead time, t dtx (ns) v out v ref 1 r fb2 r fb1 -------------- - + ?? ?? ?? ? = (eq. 2) v reftrk 2.5 d ? = (eq. 3)
isl78227 26 fn8808.2 february 24, 2016 submit document feedback pwm signal at phase node of q1 and q2 will have around 25mv at vref_trk, which is 1.56% of 1.6v reference. this will not affect the boost output voltage because of the limited bandwidth of the system. 400khz frequency is reco mmended for the pwm signal at the track pin. lower frequency at the track input is possible, but vref_trk will have higher ac ri pple. bench test evaluation is needed to make sure the output voltage is not affected by this vref_trk ac ripple. when atrk/dtrk = vcc (atrk mode), the mux connects the track pin voltage to the input of the 2-stage rc filter r 1 /c 1 /r 2 /c 2 . the track pin accepts analog signal inputs, with the gm1?s vref_trk input equal to the voltage on the track pin. the low pass filter has the same cutoff frequency of 1.75khz. if not used, the track pin should be left floating or tied to vcc and the internal vref_1.6v is working as the reference. the track function is enabled before the ss pin soft-start. the v out reference can be controlled by track inputs at start-up. after the ss pin ramps up to th e upper clamp and the vref_trk reaches 0.3v, the upper side fet is controlled to turn on gradually to achieve smooth tran sitions from dcm mode to ccm mode, of which transition duration is 100ms (when set at ccm mode). after this transition, pgood is allowed to be pulled high as long as when output voltage is in regulation (within ov/uv threshold). there is limitation of the maximum reference?s (vref_trk at figure 51 ) frequency for the boost outp ut voltage being able to track, which is determined by the boost converter?s loop bandwidth. generally, the tracking reference signal?s frequency should be 10 times lower than the boost loop crossover frequency. otherwise, the boost output voltage cannot track the tracking reference signal and the output voltage will be distorted. for example, for a boost converter with 4khz loop crossover frequency, the boost can track reference signals up to 400hz, typically. figures 23 and 24 on page 19 show performances tracking 100hz and 300hz signals. peak current mode control as shown in the figure 3 on page 7 , each phase?s pwm operation is initialized by the fi xed clock for this phase from the oscillator (refer to ? oscillator and synchronization ? on page 28 ). the clocks for phase 1 and phase 2 are 180 out-of-phase. the low-side mosfet is turned on (lgx) by the clock (after dead time delay of t dt1 ) at the beginning of a pwm cycle and the inductor current ramps up. the isl78227?s current sense amplifiers (csa) sense each phase inductor current and generates the current sense signal i senx . the i senx is added with the compensating slope and generates v rampx . when v rampx reaches the error amplifier (gm1) output voltage, the pwm comparator is triggered and lgx is turned off to shut down the low-side mosfet. the low-side mosfet stays off until the next clock signal comes for the next cycle. after the low-side mosfet is turned off, the high-side mosfet turns on after dead time t dt2 . the turn-off time of the high-side mosfet is determined by either the pwm turn-on time at the next pwm cycle or when the inductor current become zero if the diode emulation mode is selected. multiphase power conversion for an n-phase interleaved multiphase boost converter, the pwm switching of each phase is dist ributed evenly with 360/n phase shift. the total combined current ripples at the input and output are reduced where smaller input and output capacitors can be used. in addition, it is beneficial to have a smaller equivalent inductor for a faster loop desi gn. also in some applications, especially in a high current case, multiphase makes it possible to use a smaller inductor for each phase rather than one big inductor (single-phase), which is sometimes more costly or unavailable on the market at the high current rating. smaller size inductors also help to achieve low profile design. the isl78227 is a controller for 2-phase interleaved converter where the 2 phases are operating with 180 phase shift, meaning each pwm pulse is triggered 1/2 of a cycle after the start of the pwm pulse of the previous phase. figure 52 illustrates the interleaving effect on input ripple current. the ac component of the two phase currents (i l1 and i l2 ) are interleaving each other and the combined ac current ripple (i l1 + i l2 ) at input are reduced. equivalently, the frequency of the ac inductor ripple at input is 2 times of the sw itching frequency per phase. figure 51. track function block diagram track vref_2.5v 1k 2m 2m 20p 20p m u x q1 q2 r 1 r 2 c 1 c 2 2.5*d gm1 vref_1.6v fb vref_trk ss comp atrk/dtrk atrak/ dtrk ic internal circuits + + + -
isl78227 27 fn8808.2 february 24, 2016 submit document feedback to understand the reduction of th e ripple current amplitude in the multiphase circuit, examine equation 4 representing an individual phase?s peak-to-peak inductor current. in equation 4 , v in and v out are the input and the output voltages respectively, l is the single-phase inductor value and f sw is the switching frequency. the input capacitors conduct the ripple component of the inductor current. in the case of a 2-phase boost converter, the capacitor current is the sum of the ripple currents from each of the individual phases. use equation 5 to calculate the peak-to-peak ripple of the total input current which goes through the input capacitors, where k p-p can be found in figure 53 under specific duty cycle. current sharing between phases the peak current mode control inherently has current sharing capability. as shown in figure 3 on page 7 , the current sense ramp v rampx of each phase are compared to the same error amplifier?s output at the comp pin by the pwm comparators to turn off lgx when v rampx reaches comp. thus, the v rampx peaks are controlled to be the same for each phase. v rampx is the sum of instantaneous inductor current sense ramp and the compensating slope. since the compensating slopes are the same for both phases, the inductor peak current of each phase is controlled to be the same. the same mechanism applies to the case when multiple isl78227s are configured in parallel for multiphase boost converter. basically, the comp pi n of each isl78227 are tied together for each phase?s current sense ramp peak to be compared with the same comp voltage (v rampx = comp), meaning the inductor peak current of all the phases are controlled to be the same. the ? 4-phase operation ? section describes how to configure two isl78227 in parallel for a 4-phase interleaved boost converter. 4-phase operation two isl78227s can be used in parallel to achieve interleaved 4-phase operation. figure 54 shows the recommended configuration. the clkout from the master ic drives fsync of the slave ic to synchronize the switching frequencies. this achieves a 90 phase shift for the 4 phases switching and the respective comp, fb, ss, en and imon pins of the two ics are connected. clkout is 90out-of-phase with the rising edge of lg1. therefore, the two phases of the second ic are interleaved with the two phases of the first ic. figure 52. phase node and inductor-current waveforms for 2-phase converter i l1 180 t i l2 i l1 +i l2 t t i ppch v out v in C ?? v in lf sw v out ----------------------------------------------- = (eq. 4) i ppall k p-p i ppch ? = (eq. 5) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.4 5 0.5 0.55 0.6 0.65 0 .7 0.75 0.8 0.85 0.9 duty cycle figure 53. k p-p vs duty cycle k p-p figure 54. configurations for dual ic 4-phase operation master ic isl78227 slave ic isl78227 clkout fsync comp fb ss comp fb ss imon imon en en
isl78227 28 fn8808.2 february 24, 2016 submit document feedback oscillator and synchronization the switching frequency is determ ined by the selection of the frequency-setting resistor, r fsync , connected from the fsync pin to gnd. equation 6 is provided to assist in selecting the correct resistor value, where f sw is the switching frequency of each phase. figure 55 shows the relationship between r fsync and switching frequency. the isl78227 contains a phase lock loop (pll) circuit. refer to figure 4 on page 8 , the pll is compensated with a series resistor-capacitor (r pll and c pll1 ) from the pllcomp pin to gnd and a capacitor (c pll2 ) from pllcomp to gnd. at 300khz switching frequency, typical values are r pll =3.24k , c pll1 =6.8nf, c pll2 = 1nf. the pll locking time is around 0.7ms. generally, the same pll compensating network can be used in the frequency range of 50khz to 1.1mhz. with the same pll compensation network, at a frequency range higher than 500khz, the pll loop is overcompensated. however, the pll loop is stable just with slow frequency response. if a faster frequency response is required at a higher operating frequency, the pll compensation network can be tuned to have a faster response. an excel spreadsh eet to calculate the pll compensation is provided on the isl78227 web page. the isl78227?s switching frequenc y can be synchronized to the external clock signals applied at the fsync pin. the isl78227 detects the input clock?s rising ed ge and synchronizes the rising edge of lg1 to the input clock?s rising edge with a dead time delay of t dt1 . the switching frequency of each phase equals the fundamental frequency of the clock input at fsync. since the isl78227 detects only the edge of the input clock instead of its pulse width, the input clock?s pulse width can be as low as 20ns (as minimum), tens of ns, or hundreds of ns depending on the capability of the specific system to generate the external clock. the clkout pin outputs a clock si gnal with the same frequency of the per phase switching frequency. its amplitude is v cc and pulse width is 1/12 of per phase switching period (t sw /12). figure 56 shows the application example to put two isl78227 in parallel for 4-phase interleaved operation, with the master ic?s clkout being connected to the fsync pin of the slave ic. the master ic outputs clkout signal with delay of (t sw /4 - t dt1 ) after lg1_master. the slave ic fsync pin takes the clkout_master as the input and the slave?s ic lg1 is delayed by a time of (35ns + t dt1 ). therefore, the lg1_slave is delayed by (t sw /4+35ns) to lg1_master which is around 90 phase shift. with 90 phase shift between lg1 and respective lg2 for each ic, an interleaved 4-phases with 90 phase shift boost is achieved . once the isl78227 latches to being synchronized with the external clock, if the external clock on the fsync pin is removed, the switching frequency oscillator will shut down. then the part will detect pll_lock fault (refer to table 3 on page 34 ), and go to either hiccup mode or latch-off mode depending on the hic/latchoff pin configuration. if the part is set in hiccup mode, the part will restart with frequency set by the resistor at the fsync pin. the switching frequency range of the isl78227 set by r fsync or by synchronization is typically 50khz to 1.1mhz. the low end 50khz is determined by a pll_lock fault protection, which shuts down the ic when frequency is lower than 37khz typical. the phase dropping mode is not allowed with external synchronization. minimum on-time (blank time) consideration the minimum on-time (also called blank time) of lgx is the minimum on pulse width as long as lgx is turned on and it is also intended for the internal circuits to blank out the noise spikes after lgx turns on. the t minon can be programmed by a resistor at the rblank pin. the selection of the t minon depends on 2 considerations. 1. the noise spike durations after lgx turns on, which is normally in a range of tens of ns to 100ns or longer depending on the external mosfet switch ing characteristic and noise coupling path to current-sensing. 2. ensure the charging of the boot capacitor during operations of lgx operating at t minon . one typical case is an operation when the input voltage is close to the output voltage. the duty (eq. 6) r fsync 2.49x 10 ?? 10 0.505 f sw -------------- - 5.5x10 8 C C ?? ?? = 0 50 100 150 200 250 300 0 100 200 300 400 500 600 700 800 900 100 0 110 0 f sw (khz) figure 55. f sw vs r fs r fsync (k?) figure 56. timing diagram of clkout vs lg1 and fsync vs lg1 (clkout_master connected to fsync_slave) lg1_ic_master clkout_ic_master fsync_ic_slave lg1_ic_slave t sw /4 - t dt1 t1 t2 t3 35ns + t dt1
isl78227 29 fn8808.2 february 24, 2016 submit document feedback cycle is smallest at t minon and c bootx is charged by pvcc via d bootx with short duration of t minon minus the delay to pull phase low. if such operation is required, especially when a large mosfet with large q g is used to support heavy load application, larger t minon can be programmed with the resistor at the rblank pin to ensure c bootx can be sufficiently charged during minimum duty cycle operation. please refer to figure 57 for the selection of rblank resistor and t minon time. a 5k resistor is recommended as the minimum r blank resistor. operation initialization and soft-start prior to converter initialization, the en pin voltage needs to be higher than its rising threshold and the pvcc/vcc pin needs to be higher than the rising por thresh old. when these conditions are met, the controller begins in itialization and soft-start. figure 58 shows the isl78227 internal star t-up timing diagram from the power-up to soft-start. assuming input voltage is applied to the vin pin before t 1 and vcc is connected to pvcc, as shown on figure 58 , the descriptions for start-up procedure is elaborated in the following: t 1 - t 2 : the enable comparator holds the isl78227 in shutdown until the v en rises above 1.2v (typical) at the time of t 1 . during t 1 -t 2 v pvcc/vcc will gradually increase and reaches the internal power-on reset (por) rising threshold 4.5v (typical) at t 2 . t 2 - t 3 : during t 2 - t 3 , the isl78227 will go through a self-calibration process to detect certain pin configurations (hic/latch, de/phdrp, atrk/dtrak) to latch in the selected operation modes. the time duration for t 2 - t 3 is typically 195s. t 3 - t 4 : during this period, the isl7822 7 will wait until the internal pll circuits are locked to the preset oscillator frequency. when pll locking is achieved at t 4 , the oscillator will generate output at the clk_out pin. the time duration for t 3 - t 4 depends on the pllcomp pin configuration. the pll is compensated with a series resistor-capacitor (r pll and c pll1 ) from the pllcomp pin to gnd and a capacitor (c pll2 ) from pllcomp to gnd. at 300khz switching frequency, typical values are r pll = 3.24k , c pll1 = 6.8nf, c pll2 = 1nf. with this pllcomp compensation, the time duration for t 3 - t 4 is around 0.7ms. t 4 - t 5 : the pll locks the frequency t 4 and the system is preparing to soft-start. the isl78227 has one unique feature to prebias the ss pin voltage to be equal to v fb during t 4 - t 5 , which is around 50s. t 5 - t 6 : at t 5 the soft-start ramps up at the ss pin (v sspin ) and the comp voltage starts to ramp-up as well. drivers are enabled but not switching during t 5 - t 6 since the comp is still below the current sense ramp offset. the device operates in diode emulation mode during soft-start period t 5 - t 8 . the slew rate of figure 57. t minon vs rblank 0 50 100 150 200 250 300 350 400 450 500 5 1015202530354045 5055606570 r blank (k ? ) t minon (ns) en 1.2v por_r pvcc/vcc pllcomp clkout lg ug comp comp_ramp_offset vfb ss t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 pgood
isl78227 30 fn8808.2 february 24, 2016 submit document feedback the ss ramp and the duration of t 5 - t 8 are determined by the capacitor used at the ss pin. t 6 - t 7 : at t 6 comp is above the current sense ramp offset and the drivers start switching. output voltage ramps up while fb voltage is following ss ramp during this soft-start period. at t 7 , output voltage reaches the regulation level and fb voltage reaches vref_1.6v. t 7 - t 8 : ss continues ramping up until it reaches ss clamp voltage (v sspclamp ) 3.47v at t 8 indicating the ss pin ramp-up is completed. at t 8 , the isl78227 generates an internal ss_done signal, which goes high when both v sspin = v sspclamp (3.47v) and vref_trk 0.3v (as shown in figure 3 on page 7 ). this indicates the soft-start has completed. t 8 - t 9 : after t 8 , a delay time of either 0. 5ms or 100ms is inserted before the pgood pin is released high at t 9 depending on the selected mode (please refer to table 2 on page 33 ). 1. if the de/phdrp pin = gnd or float to have de mode selected, the pgood rising delay from v sspin = v sspclamp (3.47v) and vref_trk 0.3v to pgood rising is 0.5ms. 2. if the de/phdrp pin = gnd to have ccm mode selected, the pgood rising delay from v sspin = v sspclamp (3.47v) and vref_trk 0.3v to pgood rising is 100ms, during which period, the device is transitioning from de mode to ccm mode. the high-side gate ugx is controlled to gradually increase the on-time to finally merged with ccm on-time. this synchronous mosfet ?soft-on? feature is unique and ensures smooth transition fr om dcm mode to ccm mode after soft-start completes. more importantly, this ?sync fet soft-on? function eliminates the large negative current, which often occurs when starting up to a high prebiased output voltage. this feature makes the system robust for all the challenging start-up conditio ns and greatly improves the system reliability. enable to enable the device, the en pin needs to be driven higher than 1.2v (typical) by the external en able signal or resistor divider between vin and gnd. the en pin has an internal 5m (typical) pull-down resistor. also, this pin internally has a 5.2v (typical) clamp circuit with a 5k (typical) resistor in series to prevent excess voltage applied to the intern al circuits. when applying the en signal using resistor divide r from vin, internal pull-down resistance needs to be considered . also, the resistor divider ratio needs to be adjusted as its en pin input voltage may not exceed 5.2v. to disable or reset all fault status , the en pin needs to be driven lower than 1.1v (typical). when the en pin is driven low, the isl78227 turns off all of the blocks to minimize the off-state quiescent current. soft-start soft-start is implemented by an internal 5a current source charging the soft-start capacitor (c ss ) at ss to ground. the voltage on the ss pin slowly ramps up as the reference voltage for the fb voltage to follow during soft-start. typically, for boost converter before soft-start, its output voltage is charged up to be approximately a diode drop below the input voltage through the upper side mosfets? body diodes. to more accurately correlate the soft-start ramp time to the output voltage ramp time, the isl78227 ss pin voltage is prebiased with voltage equal to fb voltage before soft-start begins. the soft-start ramp time for the boost output voltage ramping from v in to the final regulated voltage v outreg , can be calculated by equation 7 , where v ref is 1.6v (vref_1.6v) with the track pin tied high: pgood signal the pgood pin is an open-drain logic output to indicate that the soft-start period is completed, the input voltage is within safe operating range and the output voltage is within the specified range. the pgood comparator monitors the fb pin to check if output voltage is within 80% to 120% of the reference voltage vref_1.6v. as described at the t 8 - t 9 duration in ? operation initialization and soft-start ? on page 29 , the pgood pin is pulled low during soft-start and it?s released high after ss_done with a 0.5ms or 100ms delay. pgood will be pulled low if any of the comparators for fb_uv, fb_ov or vin_ov is triggered fo r a duration longer than 10s. in normal operation after star t-up, under fault recovery, the pgood will be released high with the same 0.5ms delay time after the fault is removed. current sense the isl78227 peak current control architecture senses the inductor current continuously for fast response. a sense resistor is placed in series with the power inductor for each phase. the isl78227 current sense amplifiers (csa) continuously sense the respective inductor current as shown in figure 60 by sensing the voltage signal across the sense resistor r senx (where ?x? indicates the specific phase nu mber and same note applied throughout this document) . the sensed current for each active figure 59. enable block en from external en control vcc 5m 5.2v clamp - + 1.2v to internal circuits 5k vin t ss v ref 1 v in v outreg ------------------------ C c ss 5 ? a ----------- ? ?? ?? ?? ? =
isl78227 31 fn8808.2 february 24, 2016 submit document feedback phase will be used for peak current mode control loop, phase current balance, individual phase cycle-by-cycle peak current limiting (oc1), individual phase overcurrent fault protection (oc2_peak), input average consta nt current (cc) control and average overcurrent protection (oc_avg), diode emulation and phase drop control. the internal circuitry shown in figure 60 represents a single phase. this circuitry is repeated for each phase. current sense for individual phase - i senx the rc network between r senx and isenxp/n pins as shown in figure 60 is the recommended configuration. the isenxp pin should be connected to the positive potential of the r sen_chx through resistor r setx , where in figure 60 r setx is composed by r setxa plus r setxb . r set is used to set the current sense gain externally. since there is an 112a bias current sinking to each of the isenxp and isenxn pins, r biasx with same value to r setx should be placed between the isenxn pin to the low potential of the r senx , where in figure 60 r biasx is composed by r biasxa plus r biasxb . it is recommended to have r setxa = r biasxa and r setxb =r biasxb , and insert a capacitor c isenx between them as shown in figure 60 . this will form a symmetric noise filter for the small current sense signals. the differential filtering time constant equals to (r setxa +r biasxa )*c isenx . this time constant is typically selected in range of tens of ns depending on the actual noise levels. csa generates the sensed current signal i senx by forcing isenxp voltage to be equal to isenxn voltage. since r setx equals to r biasx , the voltage drop across r setx and r biasx incurred by the fixed 112a bias current cancels each other. therefore, the resulting current at csa output i senx is proportional to each phase inductor current i lx . i senx per phase can be derived in equation 11 , where i lx is the per phase current flowing through r senx . r senx is normally selected with sm allest resistance to minimize the power loss on it. with r senx selected, r setx is selected by the desired cycle-by-cycle peak current limiting level oc1 (refer to ? peak current cycle-by-cycle limiting (oc1) ? on page 35 ). average current sense for 2 phases - imon the imon pin serves to monitor the total average input current of the 2-phase boost. as shown in figure 3 on page 7 , the individual current sense signals (i senx ) are divided by 8 and summed together. a 17a offset current is added to form a current source output at the imon pin with the value calculated as shown by equation 12 . assume r sen1 = r sen2 , r set1 = r set2 , and i in = i l1 +i l2 (which is the total boost input average current): as shown in figure 4 on page 8 , a resistor r imon is placed between the imon pin and ground, which turns the current sense output from the imon pin to a voltage v imon . a capacitor c imon should be used in parallel with r imon to filter out the ripple such that v imon represents the total average input current of the 2-phase boost. v imon can be calculated using equation 14 . as shown in figure 3 on page 7 , v imon is sent to inputs of gm2 and comparators of cmp_pd and cmp_ocavg for the following functions: 1. v imon is compared with 1.6v (vref_cc) at error amplifier gm2 inputs to achieve constant current control function. the cc control threshold for the boos t input current is typically set in a way that the per phase aver age inductor current (when cc control) is lower than the per phase cycle-by-cycle peak current limiting (oc1) thre shold. please refer to ? constant current control (cc) ? on page 35 for detailed descriptions. 2. v imon is compared with phase dr opping thresholds (1.1v falling to drop phase2, 1.15v rising to add phase2). please refer to ? automatic phase dropping/adding ? on page 33 for detailed descriptions. figure 60. current-sensing block diagram v in v out l i l isenxp i senx isenxn r senx r biasxa r biasxb r setxb i senx +112a r setxa csa 112a 112a i bias i senx ic internal circuits c isenx 112a + - + - + - + - + - r setx r setxa r setxb + = (eq. 8) r biasx r biasxa r biasxb + = (eq. 9) r biasx r setx = (eq. 10) i senx i lx r senx r setx ------------------ - ? = (eq. 11) imon i l1 r ? sen1 r set1 ------------------------------- - i l2 r ? sen2 r set2 ------------------------------- - + ?? ?? ?? 0.125 ? 17 10 ? 6 C + = (eq. 12) imon i in r sen r set --------------- - 0.125 ?? 17 10 ? 6 C + = (eq. 13) v imon imon r imon ? = (eq. 14)
isl78227 32 fn8808.2 february 24, 2016 submit document feedback 3. v imon is compared with 2v for oc_avg fault protections. please refer to ? average overcurrent fault (oc_avg) protection ? on page 36 for detailed descriptions. the typical scenario when fast overloading is applied is described as the following. when large overload is suddenly applied at boost output, the phase inductor peak currents are initially limited by oc1 cycle-by-cycle, during which time the imon voltage slowly rises up due to the filter delay of r imon and c imon . when v imon reaches 1.6v, the cc loop starts to limit and control the average current to be constant, which lowers down the inductor current (as described previously, cc threshold normally is set lower than the oc1 cycle-by-cycle limiting threshold). typically tens of nf are used for c imon . in the case when a longer time delay is needed, larger c imon can be used. ? constant current control (cc) ? on page 35 has a more detailed description. adjustable slope compensation for a boost converter with peak current mode control, slope compensation is needed when duty cycle is larger than 50%. it is advised to add slope compensati on when the duty cycle is approximately 30% to 40% since a transient load step can push the duty cycle higher than the steady state level. when slope compensation is too low, the converter suffers from subharmonic oscillation, which may result in noise emissions at half the switching frequency. on the other hand, overcompensation of the slope may reduce the phase margin. therefore, proper design of the slope compensation is needed. the isl78227 features adjustable slope compensation by setting the resistor value r slope from the slope pin to ground. this function will ease the compensation design and provide more flexibility in choosing the external components. figure 61 shows the block diagram related to slope compensation. for current mode control, in theory, the compensation slope slew rate m sl needs to be larger than 50% of the inductor current down ramp slope slew rate m b . equation 15 shows the resistor value r slope at the slope pin to create a compensation ramp. where k slope is the selected gain of compensation slope over inductor down slope. for example, k slope = 1 gives the r slope value generating a compensation slope equal to inductor current down ramp slope. theoretically, the k slope needs to be larger than 0.5, but practically more th an 1.0 is used in the actual application. to cover the oper ating range, the maximum of v out and minimum of v in should be used in equation 15 to calculate the r slope . light-load efficiency enhancement for switching mode power supplies, the total loss is related to conduction loss and switching loss. the conduction loss dominates at heavy load, while the switching loss dominates at light load condition. therefore, if a multiphase converter is running at a fixed phas e number for the entire load range, the efficiency starts to drop signific antly below a certain load current. the isl78227 has selectable automatic phase dropping, cycle-by-cycle diode emulation and pulse skipping features to enhance the light-load efficiency. by observing the total input current on-the-fly and dropping an active phase, the system can achieve optimized efficiency over the entire load range. the phase dropping (ph_drop) and diode emulation (de) functions can be selected to be ac tive or inactive by setting the de/phdrp pin. please refer to table 2 for the 3 configuration modes. 1. when de/phdrp = v cc , diode emulation function is enabled, and phase drop function is disabled. 2. when de/phdrp = float, both diode emulation and phase drop functions are enabled. r slope 6.67 10 5 ? l x r setx ?? k slope v out v in C ?? r ?? senx --------------------------------------------------------------- ------------------------ - ? ?? = (eq. 15) figure 61. slope compen sation block diagram r slope slope v ramp r ramp i sl c sl vsl i slope = k2*0.5v/r slope lgx v ramp = (i senx +i sl )*r ramp i sl v ramp i sl0 i senx m b m sl m a m a1 = m a + m sl 0.5v v out l i l r senx r biasx r setx + - isenxp isenxn csa v in k1*i senx
isl78227 33 fn8808.2 february 24, 2016 submit document feedback 3. when de/phdrp = gnd, both diode emulation and phase drop functions are disabled. the part is set in continuous conduction mode (ccm). automatic phase dropping/adding when the phase drop function is enabled, the isl78227 automatically drops or adds phase 2 by comparing the v imon to the phase dropping/adding thresholds. v imon is proportional to the average input current indicating the level of the load. the phase dropping mode is not allowed with external synchronization. phase dropping when load current drops and v imon falls below 1.1v, phase 2 is disabled. for better transient response during phase dropping, the isl78227 will gradually reduce the duty cycle of the phase from steady state to zero, typically within 8 to 10 switching cycles. this gradual dropping scheme will help smooth the change of the pwm signal and stabilize the system when phase dropping happens. from equations 13 and 14 , the phase dropping current threshold level for the total 2-phase boost input current can be calculated by equation 16 . phase adding the phase adding is decided by two mechanisms listed below. the phase 2 will be added immediately if either of the two following conditions are met. 1. v imon > 1.15v, the imon pin voltage is higher than phase adding threshold 1.15v. the phase adding current threshold level for the total 2-phase boost input current can be calculated by equation 17 . 2. i senx > 80a (oc1), individual phase current triggers oc1. the first is similar to the phase dropping scheme. when the load increases causing v imon >1.15v, phase 2 will be added back immediately to support the increased load demand. since the imon pin normally has large rc filter and v imon is average current signal, this mechanism has a slow response and is intended for slow load transients. the second mechanism is intended to handle the case when load increases quickly. if the quick load increase triggers oc1 (i senx >80a) in either of the 2 phases, phase 2 will be added back immediately. after phase 2 is added, the phase dropping function will be disabled for 1.5ms. after this 1.5ms expires, the phase dropping circuit will be activated again and phase 2 can be dropped automatically as usual. diode emulation at light load condition when the diode emulation mode (de) is selected to be enabled (mode 1 and 2 in table 2 ), the isl78227 has cycle-by-cycle diode emulation operat ion at light load ac hieving discontinuous conduction mode (dcm) operation. with de mode operation, negative current is prevented and the conduction loss is reduced, therefore high efficiency can be achieved at light load conditions. diode emulation occurs during t 5 -t 8 (on figure 58 on page 29 ), regardless of the de/phdrp operating modes ( table 2 ). pulse skipping at deep light load condition if the converter enters diode emulation mode and the load is still reducing, eventually pulse skipping will occur to increase the deep light-load efficiency. either phase 1 or phase 2, or both, will be pulse skipping at these deep light load conditions. fault protections/indic ations and current limiting the isl78227 is implemented with comprehensive fault protections/indications and current limitings to design a highly reliable boost converter. most of the fault protections? response can be selected to be either hiccup or latch-off by configuring the hic/latch pin, which offers the flexibility upon the specific requirements for different applications. selectable hiccup or latch-off fault response table 3 on page 34 lists the fault protections that can have either hiccup or latch-off fault respon se determined by hic/latch pin configurations. ? when the hic/latch pin is pulled high (vcc), the fault response is in hiccup mode. ? when the hic/latch pin is pulled low (gnd), the fault response is in latch-off mode. in hiccup mode, the device will stop switching when a fault condition in table 3 on page 34 is detected, and restart from soft-start after 500ms (typical). th is operation will be repeated until fault conditions are completely removed. in latch-off mode, the device will stop switching when a fault condition in table 3 on page 34 is detected and pwm switching being kept off even after faul t conditions are removed. in latch-off status, the internal ldo is alive to keep pvcc voltage regulated. by either toggling the en pin or cycling vcc/pvcc below the por threshold w ill restart the system. table 2. ccm/de/ph_drop mode setting (de/phdrp pin) mode number (name) de/phdrp pin setting de mode phase-drop mode 1 (de) vcc enabled disabled 2 (de+ph_drop) float enabled enabled 3 (ccm) gnd disabled disabled (eq. 16) i inphdrp 1.1 r imon ------------------ - 17 10 ? 6 C C ?? ?? r set r sen --------------- - 8 ?? a ?? = i inphadd 1.15 r imon ------------------ - 17 10 ? 6 C C ?? ?? r set r sen --------------- - 8 ?? a ?? =
isl78227 34 fn8808.2 february 24, 2016 submit document feedback input overvoltage fault protection as shown in figure 3 on page 7 , the isl78227 monitors the vin pin voltage divided by 48 (vin/48) as the input voltage information. this fault detection is active at the beginning of soft-start (t 5 as shown in figure 58 on page 29 ). the vin_ov comparator compares vin/48 to 1.21v reference to detect if vin_ov fault is triggered. equivalently, when v in >58v (for 5s), vin_ov fault event is triggered. the pgood pin will be pulled low. at the same time the vin_ov fault condition is triggered, the isl78227 will respond with fault protection actions to shut down the pwm switching and enters either hiccup or latch-off mode depending on hic/latch pin configuration as described in ? selectable hiccup or latch-off fault response ? on page 33 and table 3 on page 34 . under the selection of hiccup re sponse for the vin_ov fault, when the output voltage falls down to be lower than the vin_ov threshold 58v, the device will return to normal switching through hiccup soft-start. pgood will be released to be pulled high after a 0.5ms delay. output overvoltage fault protection the isl78227 monitors the fb pin voltage to detect if output overvoltage fault (vout_ov) occurs. this fault detection is active at the beginning of soft-start (t 5 as shown in the figure 58 on page 29 ). if the fb pin voltage is higher than 120% of the voltage regulation reference vref_1.6v, the vout_ov comparator is triggered to indicate vout_ov fa ult and the pgood pin will be pulled low. at the same time, when a vout_ov fault is triggered, the isl78227 will respond with fault protection actions to shut down the pwm switching and enters either hiccup or latch-off mode depending on hic/latch pin configuration as described in ? selectable hiccup or latch-off fault response ? on page 33 and table 3 on page 34 . under the selection of hiccup re sponse for the vout_ov fault, when the output voltage falls down to be lower than the vout_ov threshold of 120%*vref_1.6v mi nus 4% hysteresis, the device will return to normal switching through hiccup soft-start. the pgood pin will be released to be pulled high after 0.5ms delay. equivalently the v out overvoltage threshold is set at the same percentage of v out target voltage v out_target (set by vref_1.6v) since the device uses the same fb voltage to regulate the output voltage wi th the same resistor divider between v out and the fb pin (refer to equation 2 on page 25 ). therefore the v out overvoltage protection threshold is set at 120% of v out_target . according to equation 2 on page 25 , the v out overvoltage protection threshold can be calculated using equation 18 . output undervoltage indication the isl78227 monitors the fb pin voltage to detect if output undervoltage (vout_uv) occurs. if the fb pin voltage is lower th an 80% of the voltage regulation reference vref_1.6v, the vout_u v comparator is triggered to indicate vout_uv occurring and the pgood pin will be pulled low. but there is no fault prot ection actions for the vout_uv condition, meaning the isl 78227 continue to keep pwm switching and normal operat ion when vout_uv occurs. table 3. fault names list for the hiccup or latch-off fault response fault name fault response hic/latch = vcc: hiccup hic/latch = gnd: latch-off descriptions vin_ov set by the hic/latch pin input over voltage fault (vin_pin >58v) protection response is hiccup when hic/latch = vcc, and latch-off when hic/latch = gnd oc_avg set by the hic/latch pin input average overcurrent fault (imon_pin >2v) protection response is hiccup when hic/latch = vcc, and latch-off when hic/latch = gnd oc2_peak set by the hic/latch pin peak overcurrent fault (i senx >105a) protection response is hiccup when hic/latch = vcc, and latch-off when hic/latch = gnd vout_ov set by the hic/latch pin output overvoltage fault (fb_pin >120%*vref_1.6v) protection response is hiccup when hic/latch = vcc, and latch-off when hic/latch = gnd pllcomp_short set by the hic/latch pin pllcomp_short fault (pllcomp_pin >1.7v) protection response is hiccup when hic/latch = vcc, and latch-off when hic/latch = gnd pll_lock set by the hic/latch pin pll loop faul t (detect the minimum frequency of 37khz as typical) protection response is hiccup when hic/latch = vcc, and latch-off when hic/latch = gnd vout ovp 1.2 1.6 ? 1 r fb2 r fb1 -------------- - + ?? ?? ?? ? = (eq. 18)
isl78227 35 fn8808.2 february 24, 2016 submit document feedback when the output voltage rises back to be above the vout_uv threshold of 80%*vref_1.6v plus 4% hysteresis, pgood will be released to be pulled high after a 0.5ms delay. equivalently, the v out undervoltage threshold is set at the same percentage of v out target voltage v out_target (set by vref_1.6v) since the device uses the same fb voltage to regulate the output voltage wi th the same resistor divider between v out and the fb pin (refer to equation 2 on page 25 ). therefore the v out undervoltage threshold is set at 80% of v out_target . according to equation 2 on page 25 , the v out undervoltage protection threshold can be calculated using equation 19 . overcurrent limiting and fault protection the isl78227 has multiple levels of overcurrent protection/limiting. each phase?s peak inductor current is protected from overcurrent conditions by limiting its peak current and the combined total current is protected on an average basis. also, each phase is implemented with instantaneous cycle-by-cycle negative current limiting (oc_neg_th = -48a). peak current cycle-by-cycle limiting (oc1) each individual phase?s inductor peak current is protected with cycle-by-cycle peak current limiting (oc1) without triggering hiccup or latch-off shutdown of the ic. the controller continuously compares the csa output current sense signal i senx (calculated by equation 11 on page 31 ) to an overcurrent limiting threshold (oc1_th = 80a ) in every cycle. when i senx reaches 80a, the respective phase?s lgx is turned off to stop inductor current further ramping up. in such a way, peak current cycle-by-cycle limiting is achieved. the equivalent cycle-by-cycle peak inductor current limiting for oc1 can be calculated by equation 20 : negative current cycle-by-cycle limiting (oc_neg) each individual phase?s inductor current is protected with cycle-by-cycle negative current limiting (oc_neg) without triggering hiccup or latch-off sh utdown of the ic. the controller continuously compares the csa output current sense signal i senx (calculated by equation 11 on page 31 ) to a negative current limiting threshold (oc_neg_th = -48a) in every cycle. when i senx falls below -48a, the respective phase?s ugx is turned off to stop the inductor current further ramping down. in such a way, negative current cycle-by-cycle limiting is achieved. the equivalent negative inductor current limiting level can be calculated by equation 21 : peak overcurrent fault (oc2_peak) protection if either of the two individual phase?s current sense signal i senx (calculated by equation 11 on page 31 ) reaches 105a (oc2_th = 105a), the peak over current fault (oc2_peak) will be triggered. the isl78227 will respond with fault protection actions to shut down the pwm switching and enters either hiccup or latch-off mode depending on hic/latch pin configuration as described in ? selectable hiccup or latch-off fault response ? on page 33 and table 3 on page 34 . this fault protection is intended to protect the device by shutdown (hiccup or latch-off) from the worst case condition where oc1 cannot limit the inductor peak current. this fault detection is active at the beginning of soft-start (t 5 as shown in the figure 58 on page 29 ). under the selection of hiccup resp onse for the oc2_peak fault, when both phases? peak current sense signal i senx no longer trip the oc2_peak thresholds (105a), the device will return to normal switching and regulation through hiccup soft-start. the equivalent inductor peak current threshold for the oc2_peak fault protection can be calculated by equation 22 : constant current control (cc) a dedicated constant average current control (cc) loop is implemented in the isl78227 to control the input current to be constant at overload conditions, which means constant input power control under certain constant input voltage. as shown in figure 3 on page 7 , the v imon represents the total input average current and is sent to the error amplifier gm2 input to be compared with the internal cc reference v ref_cc (1.6v). gm2 output is driving comp voltage through a diode d cc . thus, the comp voltage can be controlled by either gm1 output or gm2 output through d cc depending on load conditions. at normal operation wi thout overloading, v imon is lower than the v ref_cc (1.6v at default). therefore, gm2 output is high and d cc is reversely blocked and not forward conducting. in this case, the comp voltage is controlled by the voltage loop error amplifier gm1?s output to have the output voltage regulated. at input average current overloading case, when v imon reaches v ref_cc (1.6v), gm2 output falls and d cc is forward conducting, and gm2 output overrides gm1 output to drive comp. in this way the cc loop overrides the voltage loop, meaning v imon is controlled to be constant and input average constant current operation is achieved. under certain constant input voltage, input cc makes input power constant for the boost converter. compared to peak current limiting schemes, the aver age constant current control is more accurate to control the average current to be constant, which is beneficial for the user to accurately control the maximum average power for the converter to handle. the cc current threshold should be set lower than the oc1 peak current threshold with margin. ge nerally, the oc1 peak current threshold (per phase) is set 1.5 to 2 times higher than the cc current threshold (here referred to per phase average current). this matches with the physics of the power devices that normally has higher transient peak curre nt rating and lower average current ratings. the oc1 provides protection against the transient peak current. the cc controls the average current with slower vout uv 0.8 1.6 ? 1 r fb2 r fb1 -------------- - + ?? ?? ?? ? = (eq. 19) (eq. 20) i oc1x 80 10 6 C r setx r senx ------------------ - a ?? ?? = i ocnegx 48 C 10 6 C r setx r senx ------------------ - a ?? ?? = i oc2x 105 10 6 C r setx r senx ------------------ - a ?? ?? =
isl78227 36 fn8808.2 february 24, 2016 submit document feedback response, but with much more accurate control of the maximum power the system has to handle at overloading conditions. 1. when fast changing overloading occurs, since v imon has sensing delay of r imon *c imon , cc does not trip at initial transient load current until it reaches the cc reference 1.6v. oc1 will be triggered at the beginning to limit the inductor peak current cycle-by-cycle. 2. after the delay of r imon *c imon , when v imon reaches the cc reference 1.6v, cc control starts to work and limit duty cycles to reduce the inductor current and keep the sum of the two phases? inductor currents being constant. the time constant of the r imon *c imon is typically on the order of 10 times slower than the voltage loop bandwidth so that the 2 loops will not interfere with each other. cc loop is active at the beginning of soft-start. from equations 13 and 14 on page 31, the constant current control current threshold level fo r the total 2-phase boost input current can be calculated by equations 23 . average overcurrent fault (oc_avg) protection the isl78227 monitors the imon pin voltage (which represents the boost total input average curren t signal) to detect if average overcurrent (oc_avg) fault occurs. as shown in figure 3 on page 7 , the comparator cmp_ocavg compares v imon to 2v threshold to detect this fault. this fault detection is active at the beginning of soft-start (t 5 as shown in figure 58 on page 29 ). when v imon is higher than 2v, the oc_avg fault is triggered. isl78227 will respond with fault protection actions to shut down the pwm switching and enters either hiccup or latch-off mode depending on hic/latch pin configuration as described in ? selectable hiccup or latch-off fault response ? on page 33 and table 3 on page 34 . under the selection of hiccup re sponse for the oc_avg fault, when the imon voltage falls down to be lower than the 2v threshold, the device will retu rn to normal switching through hiccup soft-start. from equations 13 and 14 on page 31 , the oc_avg fault?s current threshold level for the to tal 2-phase boost input current can be calculated by equation 24 . internal die over-temperature protection the isl78227 pwm will be disabled if the junction temperature reaches +160c (typical) while the internal ldo is alive to keep pvcc/vcc biased (vcc connected to pvcc). a +15c hysteresis ensures that the device will restart with soft-start when the junction temperature falls below +145c (typical). internal 5.2v ldo the isl78227 has an internal ldo with input at vin and a fixed 5.2v/100ma output at pvcc. the internal ldo tolerates an input supply range of vin up to 55v (60v absolute maximum). a 10f, 10v or higher x7r type of ceramic capacitor is recommended between pvcc to gnd. at low vin operation when the internal ldo is saturated, the dropout voltage from the vin pin to the pvcc pin is typically 0.3v under 80ma load at pvcc as shown in the ?electrical specifications? table on page 9 . this is one of the constraints to estimate the required minimum vin voltage. the output of this ldo is mainly used as the bias supply for the gate drivers. with vcc connected to pvcc as in the typical application, pvcc also supplies othe r internal circuitry. to provide a quiet power rail to the internal analog circuitry, it is recommended to place an rc filter between pvcc and vcc. a minimum of 1f ceramic capacitor from vcc to ground should be used for noise decoupling pu rpose. since pvcc is providing noisy drive current, a small resistor like 10 or smaller between the pvcc and vcc helps to prevent the noises interfering from pvcc to vcc. figure 62 shows the internal ldo?s output voltage (pvcc) regulation versus its output current. the pvcc will drop to 4.5v (typical) when the load is 195ma (typical) because of the ldo current limiting circuits. when the load current further increases, the voltage will drop further and finally enter current foldback mode where the output current is clamped to 100ma (typical). at the worst case when ldo output is shorted to ground, the ldo output is clamped to 100ma. i incc 1.6 r imon ------------------ - 17 10 ? 6 C C ?? ?? r set r sen --------------- - 8a ?? ?? = (eq. 23) i inocavg 2 r imon ------------------ - 17 10 ? 6 C C ?? ?? r set r sen --------------- - 8a ?? ?? = (eq. 24) figure 62. internal ldo output voltage vs load 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00 0.05 0.10 0.15 0.20 0.25 iout_pvcc (a) v_pvcc (v)
isl78227 37 fn8808.2 february 24, 2016 submit document feedback based on the junction to am bient thermal resistance r ja of the package, the maximum junction temperature should be kept below +125c. however, the power losses at the ldo need to be considered, especially when the gate drivers are driving external mosfets with large gate charges. at high v in , the ldo has significant power dissipation that may raise the junction temperature where the thermal shutdown occurs. with an external pnp transistor as shown in figure 63 , the power dissipation of the internal ldo can be moved from the isl78227 to the external transistor. choose r s to be 68 so that the ldo delivers about 10ma when the exte rnal transistor begins to turn on. the external circuit increase s the minimum input voltage to approximately 6.5v. application information there are several ways to define the external components and parameters of boost regulators. this section shows one example of how to decide the parameters of the external components based on the typical application schematics as shown in figure 4 on page 8 . in the actual application, the parameters may need to be adjusted and additional components may be needed for the specific applications regarding noise, physical sizes, thermal, testing and/or other requirements. output voltage setting the output voltage (v out ) of the regulator can be programmed by an external resistor divider connecting from v out to fb and fb to gnd as shown in figure 4 on page 8 . use equation 2 on page 25 to calculate the desired v out , where v ref can be either vref_1.6v or vref_trk, whichever is lower. in the actual application, the resistor value should be decided by considering the quiescent current requirement and loop response. typically, between 4.7k to 20k will be used for the r fb1 . switching frequency switching frequency is determined by requirements of transient response time, solution size, emc/emi, power dissipation and efficiency, ripple noise level, input and output voltage range. higher frequency may improve the transient response and help to reduce the solution size. however, this may increase the switching losses and emc/emi concerns. thus, a balance of these parameters are needed when deciding the switching frequency. once the switching frequency f sw is decided, the frequency setting resistor (r fsync ) can be determined by equation 6 on page 28 . input inductor selection while the boost converter is operating in steady state continuous conduction mode (ccm), the output voltage is determined by equation 1 on page 24 . with the required inpu t and output voltage, duty cycle d can be calculated by equation 25 : where d is the on-duty of the boost low-side power transistor. under this ccm condition, the inductor peak-to-peak ripple current of each phase can be calculated as equation 26 : where t is the switching cycle 1/f sw and l is each phase inductor?s inductance. from the previous equations, the inductor value is determined by equation 27 : use equation 27 to calculate l, where values of v in , v out and i l(p-p) are based on the considerations described in following: ? one method is to select th e minimum input voltage and the maximum output voltage under long term operation as the conditions to select the inductor . in this case, the inductor dc current is the largest. ? the general rule to select inductor is to have its ripple current i l(p-p) around 30% to 50% of maximum dc current. the individual maximum dc inductor current for the 2-phase boost converter can be calculated by equation 28 , where p outmax is the maximum dc output power, eff is the estimated efficiency: using equation 27 with the two conditions listed above, a reasonable starting point for the minimum inductor value can be estimated from equation 29 , where k is typically selected as 30%. increasing the value of the inductor reduces the ripple current and therefore the ripple voltage. however, the large inductance value may reduce the converter?s response time to a load transient. this also reduces th e current sense ramp signal and may cause a noise sensitivity issue. the peak current at maximum load condition must be lower than the saturation current rating of the inductor with enough margin. in the actual design, the largest peak current may be observed at some transient conditions like the start-up or heavy load transient. therefore, the inductor?s size needs to be determined with the consideration of these conditions. to avoid exceeding figure 63. supplementing ldo current vin pvcc vin pvcc isl78227 r s d1 v in v out --------------- - C = i lp-p ?? dt vin l ---------- ?? = (eq. 26) l1 v in v out --------------- - C ?? ?? ?? v in i lp-p ?? f sw ? -------------------------------- - ? = (eq. 27) i lmax p outmax v inmin eff 2 ?? ------------------------------------------- - = (eq. 28) l min 1 v inmin v outmax -------------------------- - C ?? ?? ?? v inmin 2 eff 2 ?? p outmax kf sw ?? -------------------------------------------------- - ? = (eq. 29)
isl78227 38 fn8808.2 february 24, 2016 submit document feedback the inductor?s saturation rating, oc1 peak current limiting (refer to ? peak current cycle-by-cycle limiting (oc1) ? on page 35 ) should be selected below the inductor?s saturation current rating. output capacitor to filter the inductor current ripples and to have sufficient transient response, output capacitors are required. a combination of electrolytic and ceramic capacitors are normally used. the ceramic capacitors are used to filter the high frequency spikes of the main switching devices. in layout, these output ceramic capacitors must be placed as close as possible to the main switching devices to maintain the smallest switching loop in layout. to maintain capacitance over the biased voltage and temperature range, good quality capacitors such as x7r or x5r are recommended. the electrolytic capacitors are no rmally used to handle the load transient and output ripples. the boost output ripples are mainly dominated by the load current and output capacitance volume. for boost converter, the maximum output voltage ripple can be estimated using equation 30 , where i outmax is the load current at output, c is the total capacitance at output, and d min is the minimum duty cycle at vin max and vout min . for 2-phase boost converter, the rms current going through the output current can be calculated by equation 30 for d > 0.5, where i l is per phase inductor dc current. for d < 0.5, time domain simulation is recommended to get the accurate calculation of the input capacitor rms current. it is recommended to use multip le capacitors in parallel to handle this output rms current. input capacitor depending upon the system input power rail conditions, the aluminum electrolytic type capacitor is normally used to provide a stable input voltage. the input capacitor should be able to handle the rms current from the switching power devices. refer to equation 5 and figure 53 on page 27 to estimate the rms current the input capacitors need to handle. ceramic capacitors must be placed near the vin and pgnd pin of the ic. multiple ceramic capacitors including 1f and 0.1f are recommended. place these capacitors as close as possible to the ic. power mosfet the external mosfets driven by the isl78227 controller need to be carefully selected to optimize the design of the synchronous boost regulator. the mosfet's bv dss rating needs to have enough voltage margin against the maximum bo ost output voltage plus the phase node voltage transient spikes during switching. as the ug and lg gate drivers are 5v output, the mosfet v gs need to be in this range. the mosfet should have low total gate charge (q g ), low on-resistance (r ds(on) ) at vgs = 4.5v and small gate resistance (r g <1.5 is recommended). it is recommended that the minimum v gs threshold is higher than 1.2v but not exceeding 2.5v, in order to prevent false turn-on by noise spikes due to high dv/dt during phase node switching and maintain low r ds(on) under limitation of maximum gate drive voltage, which is 5.2v (typical) for low-side mosfet and 4.5v (typical) due to diode drop of boot diode for high-side mosfet. bootstrap capacitor the power required for high-side mosfet drive is provided by the boot capacitor connected between boot and ph pins. the bootstrap capacitor can be chosen using equation 32 : where q gate is the total gate charge of the high-side mosfet and dv boot is the maximum droop voltage across the bootstrap capacitor while turning on the high-side mosfet. though the maximum charging voltage across the bootstrap capacitor is pvcc minus the bootstrap diode drop (~4.5v), large excursions below gnd by ph node requires at least 10v rating for this ceramic capacitor. to keep enough capacitance over the biased voltage and temperature ra nge, a good quality capacitor such as x7r or x5r is recommended. resistor on bootstrap circuit in the actual application, someti mes a large ringing noise at the ph node and the boot node are observed. this noise is caused by high dv/dt phase node switching, parasitic ph node capacitance due to pcb routing an d the parasitic inductance. to reduce this noise, a resistor can be added between the boot pin and the bootstrap capacitor. a larg e resistor value will reduce the ringing noise at ph node but limi ts the charging of the bootstrap capacitor during the low-side mo sfet on-time, especially when the controller is operating at ve ry low duty cycle. also large resistance causes voltage dip at boot each time the high-side driver turns on the high-side mosfet. make sure this voltage dip will not trigger the high-side boot to ph uvlo threshold 3v (typical), especially when a mosfet with large q g is used. loop compensation design the isl78227 uses constant frequency peak current mode control architecture with a gm amp as the error amplifier. figures 64 and 65 on page 39 show the conceptual schematics and control block diagram, respectively. v outripple i outmax 1d min C ?? ? c2f sw ?? ---------------------------------------------------------- = (eq. 30) i coutrms i l 1d C ?? 2d 1 C ? ?? ? ? = (eq. 31) c boot q gate dv boot ----------------------- - ? (eq. 32)
isl78227 39 fn8808.2 february 24, 2016 submit document feedback transfer function from v c to v out transfer function from error amplifier output v c to output voltage v out g vcvo (s) can be expressed as equation 33 . the expressions of the pole s and zeros are listed below: where, ? n is the number of phases, r esr is the output capacitor?s equivalent series resistance (esr) of the total capacitors, r load is the load resistance, l eq is the equivalent inductance for multiphase boost with n number of phases, l is each phase?s inductor?s inductance. ?k isen is the current sense gain as shown in equation 34 , where r senx and r setx are per phase current sense resistor and setting resistors described in ? current sense for individual phase - i senx ? on page 31 . ? se/sn is gain of the selected compensating slope over the sensed inductor current up-ramp. it can be calculated in equation 36, where k slope is the gain of selected compensating slope over the sensed il down slope (refer to equation 15 on page 32 ). equation 33 shows that the system is mainly a single order system plus a right half zero (rhz), which commonly exists for boost converter. the main pole pps is determined by load and output capacitance and the esr zero esr is the same as buck converter. since the rhz changes with load, typically the boost converter crossover frequency is set 1/5 to 1/3 of the rhz frequency. the double pole n is at half of the f sw and has minimum effects at crossover frequency for most of the cases when the crossover frequency is fairly low. figure 64. conceptual block diagram of peak current mode controlled boost regulator - + gm v ref vo rcp ccp2 fb comp rfb2 rfb1 r 1 c 1 ccp1 roea - + - + gm slope vin rsen vout rl resr cout l gvcvo(s) he2(s) he1(s) vc vfb figure 65. conceptual control block diagram *yfyrv &xuuhqwprghfrqwuro 3rzhu6wdjh +hv (uuru$ps c 9r c 9ie c 9f .ie 9uhi 9ie g vcvo s ?? k dc 1 s ? esr ----------- - + ?? ?? 1 s ? rhz --------------- C ?? ?? ? 1 s ? p1 ---------- + ?? ?? 1 s q p ? n ? ------------------- s ? n ------ - ?? ?? 2 ++ ?? ?? ? --------------------------------------------------------------- ------------------------ - ? = (eq. 33) k dc r load 1d C ?? ? k isen ------------------------------------------ - = ? rhz r load 1d C ?? 2 ? l eq --------------------------------------------- - = ? esr 1 c out r esr ? --------------------------------- = ? pps 2 c out r load ? ---------------------------------------- - = q p 1 ? 1d C ?? s e s n ------ - ? 0.5 d ++ ? --------------------------------------------------------------- ----- - = ? n 2 f sw -------- = l eq l n --- - = k isen r senx 6500 ? r setx ------------------------------------ - = (eq. 34) (eq. 35) s e s n ------ - k slope v out v in --------------- - 1 C ?? ?? ?? ? =
isl78227 40 fn8808.2 february 24, 2016 submit document feedback compensator design generally simple type-2 compensa tor can be used to stabilize the system. in the actual application, however, an extra phase margin will be provided by a type-3 compensator. the transfer function at the erro r amplifier and its compensation network can be expressed as equation 36 . if r oea >>r cp , c cp1 >>c cp2 , and r oea = infinite, the equation can be simplified as shown in equation 37 : where, if type-3 compensation is needed, the transfer function at the feedback resistor network is: where, the total transfer function with compensation network and gain stage will be expressed: use f = /2 to convert the pole and zero expressions to frequency domain, and from equations 33 , 38 and 39 , select the compensator?s pole and zero locations. in general, as described earlier, a type-2 compensation is enough. typically the crossover frequency is set 1/5 to 1/3 of the rhz frequency. for the compensator as general rule, set p2 /2 at very low end frequency; set z2 /2 at 1/5 of the crossover frequency; set p3 /2 at the esr zero or the rhz frequency rhz /2 , whichever is lower. vcc input filter to provide a quiet power rail to the internal analog circuitry, it is recommended to place an rc filter between pvcc and vcc. a 10 resistor between pvcc and vcc and at least 1f ceramic capacitor from vcc to gnd are recommended. current sense circuit to set the current sense resistor , the voltage across the current sense resistor should be limited to within 0.3v. in a typical application, it is recommended to set the voltage across the current sense resistor in range around 30mv to 100mv for the typical load current condition. layout considerations for dc/dc converter design, the pcb layout is a very important to ensure the desired performance. 1. place input ceramic capacitors as close as possible to the ic's vin and pgnd/sgnd pins. 2. place the output ceramic capacitors as close as possible to the power mosfets. keep this loop (output ceramic capacitor and mosfets for each phase) as small as possible to reduce voltage spikes induced by the trace parasitic inductances when mosfets switching on and off. 3. place the output aluminum capacitors close to the power mosfets. 4. keep the phase node copper area small but large enough to handle the load current. 5. place the input aluminum and some ceramic capacitors close to the input inductors and power mosfets. 6. place multiple vias under the bottom pad of the ic. the bottom pad should be connected to the ground copper plane with as large an area as possible in multiple layers to effectively reduce the thermal impedance. figure 67 shows the layout example for vias in the ic bottom pad. figure 66. type-3 compensator - + gm v ref vo r cp c cp2 fb vc r fb2 r fb1 r 1 c 1 c cp1 r oea he2(s) he1(s) comp h e2 s ?? v c v fb ---------- - g m z comp = ? == (eq. 36) g m 1sr cp c cp 1 + ?? r oea 1sr cp c cp1 r o e a c cp1 c cp2 + ?? + ?? c c p 2 c cp1 r cp r o ea s 2 ++ --------------------------------------------------------------- --------------------------------------------------------------- --------------------------------------------------------------- ------------- h e2 s ?? g m 1sr cp c cp1 ?? + sc cp1 1sr cp c cp2 ?? + ?? ?? --------------------------------------------------------------- ------------------ - ? ? 1 s ------ - 1 s ? z2 --------- - + 1 s ? p2 ---------- + -------------------- ? == (eq. 37) ? p2 g m c cp1 --------------- = ? z2 1 r cp c cp1 ? ------------------------------- - = ? p3 1 r cp c cp2 ? ------------------------------- - = h e1 s ?? r fb1 r fb1 r fb2 + ----------------------------------- - 1 s ? z1 --------- - + 1 s ? p1 ---------- + -------------------- ? = (eq. 38) ? z1 1 c 1 r fb2 r 1 + ?? ? --------------------------------------------- = ? p1 1 c 1 r fb2 r fb1 ? r fb2 r 1 ? r fb1 r 1 ? ++ r fb2 r fb1 + --------------------------------------------------------------- ------------------------------------- - ? --------------------------------------------------------------- ------------------------------------------------- - = g open s ?? g vcvo s ?? h e1 s ?? h e2 s ?? ?? = (eq. 39)
isl78227 41 fn8808.2 february 24, 2016 submit document feedback 7. place the 10f decoupling ceramic capacitor at the pvcc pin and as close as possible to the ic. put multiple vias close to the ground pad of this capacitor. 8. place the 1f decoupling ceramic capacitor at the vcc pin and as close as possible to the ic. put multiple vias close to the ground pad of this capacitor. 9. keep the bootstrap capacitors as close as possible to the ic. 10. keep the driver traces as short as possible and with relatively large width (25mil to 40mil is recommended), and avoid using via or minimal number of vias in the driver path to achieve the lowest impedance. 11. place the current sense setting resistors and the filter capacitors (shown as r setxb , r biasxb and c isenx in figure 60 on page 31 ) as close as possible to the ic. keep each pair of the traces close to each other to avoid undesired switching noise injections. 12. the current-sensing traces must be laid out very carefully since they carry tiny signal s with only tens of mv. for the current-sensing traces close to the power sense resistor (r senx ), the layout pattern shown in figure 68 is recommended. assuming the r senx is placed in the top layer (red), route one current sense connection from the middle of one r senx pad in the top layer under the resistor (red trace). for the other current- sensing trace, from the middle of the other pad on r senx in top layer, after a short distance, via down to the second layer and route this trace right under the top layer current sense trace. 13. keep the current-sensing traces far from the noisy traces like gate driving traces (lgx, ugx and phx), phase nodes in power stage, bootx signals, output sw itching pulse currents, driving bias traces and input inductor ripple current signals, etc. figure 67. recommended layout pattern for vias in the ic bottom pad figure 68. recommended la yout pattern for current sense traces regulator
isl78227 42 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsidiaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8808.2 february 24, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change february 24, 2016 fn8808.2 -figure 16 on page 17: changed the label "il1" to "il2" and in figure title, changed "phase1" to "phase 2". -updated pod l32.5x5h to most recent revision with change as follows: detail "x" - added dimple dimension 0.10 0.05 back on (left side). detail "x" - changed the tolerance back (in the seating plane box) to 0.08. bottom view - removed 0.15 0.10 this is a duplicate dim with detail a. bottom view - extended the dimension li ne to the bottom of the exposed pad december 24, 2015 fn8808.1 updated expression qp and equation 35 on page 39. removed text after equation 35 on page 39 and befo re paragraph that begins with ?equation 33?. november 23, 2015 fn8808.0 initial release
isl78227 43 fn8808.2 february 24, 2016 submit document feedback package outline drawing l32.5x5h 32 lead quad flat no-lead plastic package (punch qfn with wetable flank) rev 2, 1/16 bottom view detail a side view typical recommended land pattern top view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the plated terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asmey 14.5m-1994. 5. either a mold or mark feature. 3. 4. 2. dimensions are in millimeters. 1. notes: 0.10 b a m c 4 5 pin 1 index area see detail a 0.50 0.00 min 0.08 c seating plane 0 - 12 c see detail x 0.85 0.05 0.05 max 0.25 0.05 0.15 0.05 0.15 0.10 0.40 0.10 2x 2x c a 0.10 c b 0.10 0.50 1 3 2 a b 4.75 n 0.10 2x 0.10 2x b c a c n 0.50 1 2 3 0.25 0.05 0.05 0.10 m m b a c c 3.3 pin #1 id r0.20 0.45 a c m b 3.3 (0.45) (0.45) 0.40 0.10 0.10 a c m b 5.00 4.75 5.00 0.10 4x 0.42 0.18 4x 0.42 0.18 (3.30)sq 32x (0.25) 28x (0.50) (4.80)sq 32x (0.60) detail x reference document: jedec mo220 6. 0.10 0.05 diameter

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